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5962G9654201Q9B

Description
NAND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14
Categorylogic    logic   
File Size559KB,25 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962G9654201Q9B Overview

NAND Gate, AC Series, 4-Func, 2-Input, CMOS, DIE-14

5962G9654201Q9B Parametric

Parameter NameAttribute value
package instructionDIE, DIE OR CHIP
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
seriesAC
JESD-30 codeR-XUUC-N14
JESD-609 codee0
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.0001 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialUNSPECIFIED
encapsulated codeDIE
Encapsulate equivalent codeDIE OR CHIP
Package shapeRECTANGULAR
Package formUNCASED CHIP
power supply5 V
Prop。Delay @ Nom-Sup15 ns
propagation delay (tpd)15 ns
Certification statusQualified
Schmitt triggerYES
Filter levelMIL-PRF-38535 Class Q
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
total dose500k Rad(Si) V
Base Number Matches1
REVISIONS
LTR
A
B
C
DESCRIPTION
Changes in accordance with NOR 5962-R120-97.
Changes in accordance with NOR 5962-R257-97.
Incorporate Revisions A and B. Update boilerplate to MIL-PRF-38535
requirements. – LTG
Add appendix A. – LTG
Add footnote to dose rate upset and dose rate survivability in section 1.5.
Add test circuit to figure 4. Add die detail B to appendix A. – LTG
Add device types 02 and 03. Update boilerplate. Editorial changes
throughout. – LTG
Correct radiation features in section 1.5 and add footnote 8/. Correct footnotes
2/ and 7/ in Table IA. Correct SEP test limits in table IB. Correct paragraph
4.4.4.1. Update boilerplate paragraphs to current MIL-PRF-38535
requirements. – MAA
Correct radiation features in section 1.5 and on table IA and table IB. - LTG
Add footnote 5 to figure 4. Add equivalent circuit to figure 4 - jak
DATE (YR-MO-DA)
96-12-12
97-04-22
01-10-02
APPROVED
Monica L. Poelking
Monica L. Poelking
Thomas M. Hess
D
E
F
02-01-31
03-11-20
04-08-12
Thomas M. Hess
Thomas M. Hess
Thomas M. Hess
G
09-09-09
Thomas M. Hess
H
J
11-02-22
12-07-09
David Corbett
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
J
15
J
16
J
17
J
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DSCC FORM 2233
APR 97
DRAWING APPROVAL DATE
96-05-31
REVISION LEVEL
J
19
J
20
J
21
J
1
J
22
J
2
J
23
J
3
J
4
J
5
J
6
J
7
J
8
J
9
J
10
J
11
J
12
J
13
J
14
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, QUADRUPLE
2-INPUT NAND SCHMITT TRIGGER, MONOLITHIC
SILICON
SIZE
CAGE CODE
J
A
67268
SHEET
1 OF 23
5962-96542
5962-E396-12
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