ICS557-05A
Quad Differential PCI-Express Clock Source
Description
The ICS557-05A is a spread-spectrum clock generator
that supports PCI-Express requirements. It is used in
PC or embedded systems to substantially reduce
electro-magnetic interference (EMI). The device
provides four differential HCSL or LVDS high-frequency
outputs with spread spectrum capability. The output
frequency and spread type are selectable using
external pins.
Features
•
•
•
•
•
•
•
•
•
•
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Packaged in 20-pin TSSOP
Available in Pb (lead) free package
Supports PCI-Express applications
Four differential spread spectrum clock outputs
Spread spectrum for EMI reduction
Uses external 25 MHz clock or crystal input
Power down pin turns off chip
OE control tri-states outputs
Spread and frequency selection via external pins
Spread Bypass option available
Industrial temperature range available
Block Diagram
VDD
2
PD
OE
SEL[2:0]
3
Spread
Spectrum/
Output
clock
selection
Spread
Spectrum
Circuitry
CLKOUTA
25 MHz
crystal or
clock
X1
Clock
Oscillator
X2
CLKOUTA
CLKOUTB
PLL Clock
Synthesis
CLKOUTB
CLKOUTC
CLKOUTC
CLKOUTD
CLKOUTD
2
GND
Rr(IREF)
Optional tuning crystal
capacitors
MDS 557-05A E
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 011606
tel (408) 297-1201
●
www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Pin Assignment
VDDXD
S0
S1
S2
X1
X2
PD
OE
GNDXD
IREF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLKA
CLKA
CLKB
CLKB
GNDODA
VDDODA
CLKC
CLKC
CLKD
CLKD
20-pin (173 mil) TSSOP
Spread Spectrum Selection Table
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Spread%
-0.5
-1.0
-1.5
No Spread
-0.5
-1.0
-1.5
No Spread
Spread Type
Down
Down
Down
Not Applicable
Down
Down
Down
Not Applicable
Output
Frequency (MHz)
100
100
100
100
200
200
200
200
MDS 557-05A E
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 011606
tel (408) 297-1201
●
www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
VDDXD
S0
S1
S2
X1
X2
PD
OE
GND
IREF
CLKD
CLKD
CLKC
CLKC
VDDODA
GND
CLKB
CLKB
CLKA
CLKA
Pin
Type
Power
Input
Input
Input
Input
Output
Input
Input
Power
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Connect to +3.3 V digital supply.
Pin Description
Spread spectrum select pin #0. See table above. Internal pull-up resistor.
Spread spectrum select pin #1. See table above Internal pull-up resistor.
Spread spectrum select pin #2. See table above. Internal pull-up resistor.
Crystal connection. Connect to a fundamental mode crystal or clock input.
Crystal connection. Connect to a fundamental mode crystal or leave open.
Powers down all PLL’s and tri-states outputs when low. Internal pull-up resistor.
Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
Connect to digital ground.
Precision resistor attached to this pin is connected to the internal current reference.
Selectable 100/200 MHz spread spectrum differential Compliment output clock D.
Selectable 100/200 MHz spread spectrum differential True output clock D.
Selectable 100/200 MHz spread spectrum differential Compliment output clock C.
Selectable 100/200 MHz spread spectrum differential True output clock C.
Connect to +3.3 V analog supply.
Connect to analog ground.
Selectable 100/200 MHz spread spectrum differential Compliment output clock B.
Selectable 100/200 MHz spread spectrum differential True output clock B.
Selectable 100/200 MHz spread spectrum differential Compliment output clock A.
Selectable 100/200 MHz spread spectrum differential True output clock A.
MDS 557-05A E
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 011606
tel (408) 297-1201
●
www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Load Resistors R
L
Since the clock outputs are open source outputs, 50
ohm external resistors to ground are to be connected at
each clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-05A.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
External Components
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01
µF
should be connected between VDD and GND
pairs (1,9 and 15,16) as close to the device as possible.
On chip capacitors-
Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C
L
-12)*2 in this equation,
C
L
=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50Ω, then Rr =
475Ω (1%), providing IREF of 2.32 mA, output current
(I
OH
) is equal to 6*IREF.
MDS 557-05A E
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 011606
tel (408) 297-1201
●
www.icst.com
ICS557-05A
Quad Differential PCI-Express Clock Source
Output Structures
IREF
=2.3 mA
6*IREF
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the
ICS557-05A.This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 557-05A E
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 011606
tel (408) 297-1201
●
www.icst.com
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