Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in
Table 10-4,
Flash Endurance is 10,000 cycles. Addressed additional grammar
issues.
Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in
Table 10-5.
Replacing TBD Typical Min with values in
Table 10-17.
Editing grammar, spelling, consistency of
language throughout family. Updated values in Regulator Parameters,
Table 10-9,
External Clock
Operation Timing Requirements
Table 10-13,
SPI Timing,
Table 10-18,
ADC Parameters,
Table 10-24,
and IO Loading Coefficients at 10MHz,
Table 10-25.
Updated values in Power-On Reset Low Voltage,
Table 10-6.
Correcting package pin numbers in
Table 2-2,
PhaseA0
changed from 38 to 52,
PhaseB0
changed
from 37 to 51,
Index0
changed from 36 to 50, and
Home0
changed from 35 to 49. All pin changes in
Table 2-2 were do to data entry errors - This package pin-out has not changed
Added
Part 4.8,
added addition text to
Part 6.9
on POR reset, added the word “access” to FM Error
Interrupt in
Table 4-3,
removed min and max numbers; only documenting Typ. numbers for LVI in
Table 10-6.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data. Corrected typo in
Table 10-3
in
Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; changed example in
Part
2.2;
added note on V
REFH
and V
REFLO
in
Table 2-2
and
Table 11-1;
added note to Vcap pin in
Table 2-2;
corrected typo FIVAL1 and FIVAH1 in
Table 4-12;
removed unneccessary notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added ADC calibration information to
Table 10-24
and new graphs in
Figure 10-21.
Clarification to
Table 10-23,
corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8123 information; edited to indicate differences in 56F8323 and 56F8123.Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of
electrical tables for consistency throughout the family. Clarified I/O power description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3
.
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev. 11.0
Please see http://www.freescale.com/semiconductors for the most current Data Sheet revision.
56F8323 Technical Data, Rev. 11.0
2
Freescale Semiconductor
Preliminary
56F8323/56F8123 General Description
Note:
Features in italics are NOT available in the 56F8123 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• One FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 27 GPIO lines
• 64-pin LQFP Package
RESET
5
6
3
3
OCR_DIS
V
CAP
4
V
DD
4
4
V
SS
V
DDA
2
V
SSA
PWM Outputs
Current Sense Inputs
Fault Inputs
PWMA or
SPI1 or
GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36
−>
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
4
4
5
AD0
AD1
VREF
TEMP_SENSE
PAB
PDB
CDBR
CDBW
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
R/W Control
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIO B
System Bus
Control
IPBus Bridge (IPBB)
3
Quad
Timer C or
SCI0 or
GPIOC
FlexCAN or
GPIOC
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
Decoding
Peripherals
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Watchdog
Interrupt
Controller
System
O
Integration
R
Module
P
O
Clock
S
Generator*
C
XTAL or GPIOC
EXTAL or GPIOC
IRQA
*Includes On-Chip
Relaxation Oscillator
56F8323/56F8123 Block Diagram
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
56F8323/56F8123 Features . . . . . . . . . . . . . 5
Device Description . . . . . . . . . . . . . . . . . . . . 7
Award-Winning Development Environment . 8
Architecture Block Diagram . . . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . . . 13
Data Sheet Conventions . . . . . . . . . . . . . . 13
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 101
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 101
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 101
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 103
Part 9: Joint Test Action Group (JTAG) . 103
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .103
Part 2: Signal/Connection Descriptions . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part 10: Specifications . . . . . . . . . . . . . . . 104
10.1. General Characteristics . . . . . . . . . . . . . .104
10.2. DC Electrical Characteristics . . . . . . . . . . 108
10.3. AC Electrical Characteristics . . . . . . . . . . 112
10.4. Flash Memory Characteristics . . . . . . . . . 113
10.5. External Clock Operation Timing . . . . . . . 114
10.6. Phase Locked Loop Timing . . . . . . . . . . .115
10.7. Crystal Oscillator Parameters . . . . . . . . . 115
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 117
10.9. Serial Peripheral Interface (SPI) Timing . . 119
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 122
10.11. Quadrature Decoder Timing . . . . . . . . . . 122
10.12. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 123
10.13. Controller Area Network (CAN) Timing . 124
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 124
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 126
10.16. Equivalent Circuit for ADC Inputs . . . . . .129
10.17. Power Consumption . . . . . . . . . . . . . . . . 129
Part 3: On-Chip Clock Synthesis (OCCS) . . 28
3.1.
3.2.
3.3.
3.4.
3.5.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Operation . . . . . . . . . . . . . .
Use of On-Chip Relaxation Oscillator . . . . .
Internal Clock Operation . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
30
31
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 31
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers . . . .
Factory Programmed Memory . . . . . . . . . .
31
31
32
35
35
37
38
55
Part 5: Interrupt Controller (ITCN) . . . . . . . . 55
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
56
56
58
58
59
81
Part 11: Packaging . . . . . . . . . . . . . . . . . . 131
11.1. 56F8323 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 131
11.2. 56F8123 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 133
Part 6: System Integration Module (SIM) . . 82
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . .
Operating Mode Register . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . . . . .
Clock Generation Overview . . . . . . . . . . . .
Power-Down Modes . . . . . . . . . . . . . . . . . .
Stop and Wait Mode Disable Function . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
82
83
83
84
96
96
97
97
Part 12: Design Considerations . . . . . . . . 136
12.1. Thermal Design Considerations . . . . . . . . 136
12.2. Electrical Design Considerations . . . . . . . 137
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .138
Part 13: Ordering Information . . . . . . . . . 139
Part 7: Security Features . . . . . . . . . . . . . . . 98
7.1. Operation with Security Enabled . . . . . . . . 98
7.2. Flash Access Blocking Mechanisms . . . . . 98
56F8323 Technical Data, Rev. 11.0
4
Freescale Semiconductor
Preliminary
56F8323/56F8123 Features
Part 1 Overview
1.1 56F8323/56F8123 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Hybrid Controller Core
Efficient 16-bit 56800E family engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8323 and 56F8123 devices.
Table 1-1 Device Differences
Feature
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
56F8323
60MHz/60 MIPS
4KB
8KB
1x6
1
1x4
1
—
56F8123
40MHz/40 MIPS
Not Available
Not Available
Not Available
Not Available
Not Available
Not Available
10
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
Preliminary
5
DSP and ARM Processors
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