5962-9858701QZX datasheet, PDF

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5962-9858701QZX: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, QFP-132; CategoryThe embedded processor and controller Microcontrollers and processors; File Size923KB，119 Pages; ManufacturerCobham Semiconductor Solutions

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5962-9858701QZX Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, QFP-132

5962-9858701QZX Parametric

Parameter Name	Attribute value
Parts packaging code	QFP
package instruction	QFF,
Contacts	132
Reach Compliance Code	unknown
Address bus width	16
boundary scan	YES
maximum clock frequency	24 MHz
letter of agreement	MIL STD 1553A; MIL STD 1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	S-XQFP-F132
length	24.13 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	132
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	3.302 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	QUAD
width	24.13 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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Standard Products

UT69151 SµMMIT

RTE

Product Handbook

June 1999

FEATURES

Comprehensive MIL-STD-1553 dual redundant Remote

Terminal (RT) with integrated bus transceivers, Memory,

and Memory Management Unit (MMU)

MIL-STD-1553B, Notice II RT

- Internal command illegalization

- 16-bit read/write time-tag with user-defined resolution

- Subaddress data buffering

Programmable interrupt architecture with automatic

interrupt logging available

Autonomous operation

- External initialization bus

- Ideal for low cost remote terminals

Internal Memory Management Unit (MMU) interfaces host

subsystem to 64Kbit SRAM

- Wait state and zero-wait state configurations

Built-In Test capability

Supports IEEE Standard 1149.1 (JTAG)

Flexible power supply configurations

- +5-volt only operation

Flexible packaging offering:

- 139-pin pingrid array (PGA)

- 140-lead flatpack

- 132-lead flatpack

Standard Microcircuit Drawing 5962-98587

MODE

STATUS

JTAG

INTERRUPTS

CHA

TRANSCEIVER

CHA

DATA

SµMMIT

Protocol

Handler

CHB

TRANSCEIVER

CHB

MEMORY

MMU

INTERFACE

CONTROL

Auto-Init Bus

ADDRESS

REMOTE

TERMINAL

ADDRESS

Figure 1. UT69151 SµMMIT RTE Block Diagram

2.1.2 Operational Status Register (Read/Write) - Register 1

This register reflects pertinent status information for the SµΜΜIT RTE and is not reset to 0000 (hex) on MRST. Instead, the register

reflects the actual stimulus applied to input pins RTA(4:0), RTPTY, A/B STD, and LOCK. Assertion of the LOCK input prevents

the modification of the remote terminal address, mode selects, and A or B Standard. In this case, a write to this register’s most

significant nine bits is meaningless. If LOCK is negated, a read of this register reflects the information written into this register’s

most significant nine bits.

Note: To make changes to the SµΜΜIT RTE and this register, the STEX bit (Bit 15 in Register 0) must be logic zero.

Bit

Mnemonic

Description

Number

RTA4

Terminal Address Bit 4. This bit is the most significant bit of the remote terminal address.

This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is

active.

Terminal Address Bit 3. This bit is Bit 3 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

Terminal Address Bit 2. This bit is Bit 2 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

Terminal Address Bit 1. This bit is Bit 1 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

Terminal Address Bit 0. This bit is the least significant bit of the remote terminal address.

This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is

active.

Terminal Address Parity Bit. This bit is appended to the remote terminal address bus

(RTA(4:0)) to supply odd parity. The SµΜΜIT RTE requires odd parity for proper

operation. This bit is latched on the rising edge of MRST and is a read only bit if the

LOCK pin is active.

Always set this bit to logical zero.

Always set this bit to logical one.

Military Standard 1553A or 1553B Standard. This bit determines whether the SµΜΜIT

RTE will be set to operate under MIL-STD-1553A or B. Assertion of this bit enables the

XMTSW bit (Bit 0 of the Control Register). Negation of this bit automatically allows the

SµΜΜIT RTE to operate under the MIL-STD-1553B protocol. This bit is latched on the

rising edge of MRST and is a read only bit if the LOCK pin is active. See section 2.9 for

further definition.

LOCK Pin. This read-only bit reflects the inverted state of input pin LOCK and is latched

on the rising edge of MRST.

AUTOEN Pin. This read-only bit reflects the inverted state of input pin AUTOEN.

Assertion of this input enables SµΜΜIT RTE auto-initialization.

SSYSF Pin. This read-only bit reflects the inverted state of the input pin SSYSF.

SµΜΜIT RTE Executing. This read-only bit indicates whether the SµΜΜIT RTE is

presently executing or whether it is idle. A logic one indicates that the SµΜΜIT RTE is

executing; logic zero indicates that the SµΜΜIT RTE is idle.

Terminal Address Parity Fail. This bit indicates the observance of a terminal address parity

error. The SµΜΜIT RTE checks for odd parity. This read only bit reflects the parity of

Operational Status Register bits 15-10, and is latched on the rising edge of MRST.

RTA3

RTA2

RTA1

RTA0

RTPTY

N/A

Logical one

A/B STD

LOCK

AUTOEN

SSYSF

TAPF

SµMMIT RTE

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