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5962R9655803VXC

Description
Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDFP16, CERAMIC, DFP-16
Categorylogic    logic   
File Size218KB,10 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962R9655803VXC Overview

Parallel In Serial Out, AC Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDFP16, CERAMIC, DFP-16

5962R9655803VXC Parametric

Parameter NameAttribute value
package instructionDFP,
Reach Compliance Codeunknown
Counting directionRIGHT
seriesAC
JESD-30 codeR-CDFP-F16
JESD-609 codee4
Logic integrated circuit typePARALLEL IN SERIAL OUT
Number of digits8
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)25 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.6 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose100k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.731 mm
Base Number Matches1
UT54ACS165E
Radiation-Hardened
8-Bit Parallel Shift Registers
January 2004
www.aeroflex.com/radhard
FEATURES
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversions
0.6µm
CRH CMOS Process
- Latchup immune
High speed
Low power consumption
Wide operating power supply from 3.0V to 5.5V
Available QML Q or V processes
16-lead flatpack
FUNCTION TABLE
INPUTS
SH/ CLK CLK SER PARALLEL
LD INH
A ... H
INTERNAL OUTPUTS
OUTPUTS
Q
A
Q
B
Q
H
Q
H
h
L
H
H
H
H
X
L
L
L
H
X
L
X
X
H
L
X
a ... h
X
X
X
X
a
Q
A
H
L
Q
A
b
Q
B
Q
A
Q
A
Q
B
h
Q
H
Q
G
Q
G
Q
H
Q
H
Q
G
Q
G
Q
H
X
DESCRIPTION
The UT54ACS165E is an 8-bit serial shift register that, when clocked,
shifts the data toward serial output Q
H
. Parallel-in access to each stage
is provided by eight individual data inputs that are enabled by a low
level at the SH/LD input. The devices feature a clock inhibit function
and a complemented serial output Q
H
.
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low. The functions of
the CLK and CLK INH (clock inhibit) inputs are interchangeable.
Since a low CLK input and a low-to-high transition of CLK INH will
also accomplish clocking, CLK INH should be changed to the high
level only while the CLK input is high. Parallel loading is disabled
when SH/LD is held high. Parallel inputs to the registers are enabled
while SH/LD is low independently of the levels of CLK, CLK INH or
SER inputs.
The device is characterized over the full military temperature range of
-55°C to +125°C.
Note:
1. Q
n
= The state of the referenced output one setup time prior to the Low-to-
High clock transition.
LOGIC SYMBOL
(1)
SH/LD
(15)
CLK INH
(2)
CLK
(10)
SER
(11)
A
(12)
B
(13)
C
(14)
D
(3)
E
(4)
F
(5)
G
(6)
H
SRG8
C1 (LOAD)
≥1
C2/
PINOUT
16-Lead Flatpack
Top View
SH/LD
CLK
E
F
G
H
Q
H
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK INH
D
C
B
A
SER
Q
H
2D
1D
1D
1D
(9)
Q
(7)
H
Q
H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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