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5962F9655401QXA

Description
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16
Categorylogic    logic   
File Size250KB,10 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962F9655401QXA Overview

Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, CDFP16, BOTTOM-BRAZED, CERAMIC, DFP-16

5962F9655401QXA Parametric

Parameter NameAttribute value
package instructionDFP,
Reach Compliance Codeunknown
Counting directionUP
seriesAC
JESD-30 codeR-CDFP-F16
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Operating modeSYNCHRONOUS
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)24 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose300k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.731 mm
minfmax77 MHz
Base Number Matches1
Standard Products
UT54ACS163/UT54ACTS163
4-Bit Synchronous Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Synchronously programmable
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS163 - SMD 5962-96554
UT54ACTS163 - SMD 5962-96555
DESCRIPTION
The UT54ACS163 and the UT54ACTS163 are synchronous
presettable 4-bit binary counters that feature internal carry look-
ahead logic for high-speed counting designs. Synchronous op-
eration occurs by having all flip-flops clocked simultaneously
so that the outputs change coincident with each other when in-
structed by the count-enable inputs and internal gating. A buff-
ered clock input triggers the four flip-flops on the rising (posi-
tive-going) edge of the clock input waveform.
The counters are fully programmable (i.e., they may be preset
to any number between 0 and 15). Presetting is synchronous;
applying a low level at the load input disables the counter and
causes the outputs to agree with the load data after the next clock
pulse.
The clear function is synchronous and a low level at the clear
input sets all four of the flip-flop outputs low after the next clock
pulse. This synchronous clear allows the count length to be mod-
ified by decoding the Q outputs for the maximum count desired.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, or LOAD) that modify the operat-
ing mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
1
PINOUTS
16-Pin DIP
Top View
CLR
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
16-Lead Flatpack
Top View
CLR
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
LOGIC SYMBOL
(1)
CLR
(9)
LOAD
ENT
ENP
CLK
A
B
C
D
(10)
(7)
(2)
(3)
(4)
(5)
(6)
CTRDIV 16
5CT=0
M1
M2
3CT = 15
G3
G4
C5/2,3,4+
1,5D
(1)
(2)
(4)
(8)
(14)
(13)
(12)
(11)
Q
A
Q
B
Q
C
Q
D
(15)
RCO
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
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