5962H9654101QXA datasheet, PDF

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5962H9654101QXA: DescriptionJ-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16; Categorylogic logic; File Size167KB，19 Pages; ManufacturerCobham PLC

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5962H9654101QXA Overview

J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16

5962H9654101QXA Parametric

Parameter Name	Attribute value
package instruction	DFP, FL16,.3
Reach Compliance Code	unknown
ECCN code	3A001.A.1.A
series	ACT
JESD-30 code	R-XDFP-F16
JESD-609 code	e0
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-KBAR FLIP-FLOP
MaximumI(ol)	0.008 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Prop。Delay @ Nom-Sup	27 ns
propagation delay (tpd)	27 ns
Certification status	Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	2.921 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	1M Rad(Si) V
Trigger type	POSITIVE EDGE
width	6.731 mm
minfmax	62 MHz
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Changes in accordance with NOR 5962-R144-97.

Incorporate Revision A. Update boilerplate to MIL-PRF-38535 requirements. –

LTG

Correct the title to accurately describe the device function. Change figure 4,

switching waveforms and test circuit. Update boilerplate to the latest

MIL-PRF-38535 requirements. - jak

Update radiation features in section 1.5 and SEP test limits in table IB. Correct

function of pin 10 in figure 1. Update boilerplate paragraphs as specified in

MIL-PRF-38535 requirements. - MAA

DATE (YR-MO-DA)

96-12-10

01-09-04

07-11-07

APPROVED

Monica L. Poelking

Thomas M. Hess

Thomas M Hess

11-04-19

David J. Corbett

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Thanh V. Nguyen

CHECKED BY

Thanh V. Nguyen

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil/

APPROVED BY

Monica L. Poelking

DRAWING APPROVAL DATE

96-04-12

REVISION LEVEL

MICROCIRCUIT, DIGITAL, ADVANCED CMOS,

RADIATION HARDENED, DUAL J-K FLIP-FLOP

WITH CLEAR AND PRESET, TTL COMPATIBLE

INPUTS, MONOLITHIC SILICON

SIZE

CAGE CODE

AMSC N/A

67268

5962-96541

SHEET 1 OF 18

DSCC FORM 2233

APR 97

5962-E221-11

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 -

MIL-STD-1835 -

Test Method Standard Microcircuits.

Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

(Copies of these documents are available online at

https://assist.daps.dla.mil/quicksearch/

or from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

ASTM INTERNATIONAL (ASTM)

ASTM F1192

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion

Irradiation of semiconductor Devices.

(Copies of these documents are available online at

http://www.astm.org

or from ASTM International, 100 Barr Harbor Drive,

P.O. Box C700, West Conshohocken, PA, 19428-2959).

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.5 Switching waveforms and test circuits. The switching waveforms and test circuits shall be as specified on figure 4.

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96541

SHEET

3.2.6 Irradiation test connections. The irradiation test connections shall be as specified in table III.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the

full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are described in table IA.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of

supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-

PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of

product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime 's agent,

and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore

documentation shall be made available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 38 (see MIL-PRF-38535, appendix A).

STANDARD

MICROCIRCUIT DRAWING

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96541

SHEET

5962H9654101QXA Related Products

	5962H9654101QXA	5962H9654101QXC	5962H9654101VXC	5962H9654101QEA	5962H9654101VEC	5962H9654101VXA	5962H9654101QEC	5962H9654101VEA
Description	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16
package instruction	DFP, FL16,.3	DFP, FL16,.3	DFP, FL16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DFP, FL16,.3	SIDE BRAZED, CERAMIC, DIP-16	SIDE BRAZED, CERAMIC, DIP-16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A	3A001.A.1.A
series	ACT	ACT	ACT	ACT	ACT	ACT	ACT	ACT
JESD-30 code	R-XDFP-F16	R-XDFP-F16	R-XDFP-F16	R-XDIP-T16	R-XDIP-T16	R-XDFP-F16	R-XDIP-T16	R-XDIP-T16
JESD-609 code	e0	e4	e4	e0	e4	e0	e4	e0
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP
MaximumI(ol)	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A
Number of digits	2	2	2	2	2	2	2	2
Number of functions	2	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DFP	DFP	DIP	DIP	DFP	DIP	DIP
Encapsulate equivalent code	FL16,.3	FL16,.3	FL16,.3	DIP16,.3	DIP16,.3	FL16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK	IN-LINE	IN-LINE	FLATPACK	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns
propagation delay (tpd)	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns	27 ns
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified	Qualified
Filter level	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535V;38534K;883S	38535Q/M;38534H;883B	38535V;38534K;883S	38535V;38534K;883S	38535Q/M;38534H;883B	38535V;38534K;883S
Maximum seat height	2.921 mm	2.921 mm	2.921 mm	5.08 mm	5.08 mm	2.921 mm	5.08 mm	5.08 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	NO	NO	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	GOLD	GOLD	TIN LEAD	GOLD	TIN LEAD	GOLD	TIN LEAD
Terminal form	FLAT	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
total dose	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V	1M Rad(Si) V
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	6.731 mm	6.731 mm	6.731 mm	7.62 mm	7.62 mm	6.731 mm	7.62 mm	7.62 mm
minfmax	62 MHz	62 MHz	62 MHz	62 MHz	62 MHz	62 MHz	62 MHz	62 MHz
Base Number Matches	1	1	1	1	1	1	1	1

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