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5962H9652601VXA

Description
NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14
Categorylogic    logic   
File Size499KB,21 Pages
ManufacturerCobham PLC
Download Datasheet Parametric Compare View All

5962H9652601VXA Overview

NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14

5962H9652601VXA Parametric

Parameter NameAttribute value
package instructionDFP, FL14,.3
Reach Compliance Codeunknown
ECCN code3A001.A.1.A
seriesAC
JESD-30 codeR-CDFP-F14
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.008 A
Number of functions2
Number of entries4
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
Prop。Delay @ Nom-Sup15 ns
propagation delay (tpd)15 ns
Certification statusQualified
Schmitt triggerNO
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose1M Rad(Si) V
Base Number Matches1
REVISIONS
LTR
A
B
C
DESCRIPTION
Changes in accordance with NOR 5962-R108-97. – TVN
Changes in accordance with NOR 5962-R086-98. – CFS
Add limit for linear energy threshold (LET) with no latch-up in section 1.5.
Update the boilerplate to the requirements of MIL-PRF-38535. Editorial
changes throughout. – TVN
Update boilerplate paragraphs and radiation paragraphs 4.4.4.1 – 4.4.4.4 to
the current MIL-PRF-38535 requirements. - LTG
DATE (YR-MO-DA)
96-12-10
98-03-31
05-08-24
APPROVED
Monica L. Poelking
Monica L. Poelking
Thomas M. Hess
D
12-05-17
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
D
15
D
16
D
17
D
18
REV
SHEET
PREPARED BY
Larry T. Gauder
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DSCC FORM 2233
APR 97
DRAWING APPROVAL DATE
96-04-03
REVISION LEVEL
D
19
D
20
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, ADVANCED CMOS, DUAL 4-INPUT
NAND GATE, MONOLITHIC SILICON
SIZE
CAGE CODE
D
A
67268
SHEET
1 OF 20
5962-96526
5962-E321-12

5962H9652601VXA Related Products

5962H9652601VXA 5962H9652601Q9A 5962H9652601VXC 5962H9652601QCC 5962H9652601QXC 5962H9652601QXA 5962H9652601V9A 5962H9652601VCC 5962H9652601VCA 5962H9652601QCA
Description NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, DIE-24 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, DIP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDFP14, CERAMIC, DFP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, DIE-24 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, DIP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, DIP-14 NAND Gate, AC Series, 2-Func, 4-Input, CMOS, CDIP14, CERAMIC, DIP-14
package instruction DFP, FL14,.3 DIE, DIE OR CHIP DFP, FL14,.3 DIP, DIP14,.3 DFP, FL14,.3 DFP, FL14,.3 DIE, DIE OR CHIP CERAMIC, DIP-14 CERAMIC, DIP-14 DIP, DIP14,.3
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknown unknow
ECCN code 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A
series AC AC AC AC AC AC AC AC AC AC
JESD-30 code R-CDFP-F14 R-XUUC-N24 R-CDFP-F14 R-GDIP-T14 R-CDFP-F14 R-CDFP-F14 R-XUUC-N24 R-GDIP-T14 R-GDIP-T14 R-GDIP-T14
JESD-609 code e0 e0 e4 e4 e4 e0 e0 e4 e0 e0
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE NAND GATE
MaximumI(ol) 0.008 A 0.0001 A 0.008 A 0.008 A 0.008 A 0.008 A 0.0001 A 0.008 A 0.008 A 0.008 A
Number of functions 2 2 2 2 2 2 2 2 2 2
Number of entries 4 4 4 4 4 4 4 4 4 4
Number of terminals 14 24 14 14 14 14 24 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
Package body material CERAMIC, METAL-SEALED COFIRED UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED UNSPECIFIED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
encapsulated code DFP DIE DFP DIP DFP DFP DIE DIP DIP DIP
Encapsulate equivalent code FL14,.3 DIE OR CHIP FL14,.3 DIP14,.3 FL14,.3 FL14,.3 DIE OR CHIP DIP14,.3 DIP14,.3 DIP14,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK UNCASED CHIP FLATPACK IN-LINE FLATPACK FLATPACK UNCASED CHIP IN-LINE IN-LINE IN-LINE
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
propagation delay (tpd) 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns
Certification status Qualified Qualified Qualified Qualified Qualified Qualified Qualified Qualified Qualified Qualified
Schmitt trigger NO NO NO NO NO NO NO NO NO NO
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class Q MIL-PRF-38535 Class V MIL-PRF-38535 Class Q MIL-PRF-38535 Class Q MIL-PRF-38535 Class Q MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class Q
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES NO YES YES YES NO NO NO
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal surface TIN LEAD TIN LEAD GOLD GOLD GOLD TIN LEAD TIN LEAD GOLD TIN LEAD TIN LEAD
Terminal form FLAT NO LEAD FLAT THROUGH-HOLE FLAT FLAT NO LEAD THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal location DUAL UPPER DUAL DUAL DUAL DUAL UPPER DUAL DUAL DUAL
total dose 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V
Prop。Delay @ Nom-Sup 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns -
Terminal pitch 1.27 mm - 1.27 mm 2.54 mm 1.27 mm 1.27 mm - 2.54 mm 2.54 mm 2.54 mm
Base Number Matches 1 1 1 1 1 1 1 1 1 -

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