The 16-bit wide UT54ACS164245S MultiPurpose transceiver
is built using UTMC’s Commercial RadHard
TM
epitaxial
CMOS technology and is ideal for space applications. This high
speed, low power UT54ACS164245S transceiver is designed
to perform multiple functions including: asynchronous two-
way communication, signal buffering, voltage translation, and
cold sparing. With V
DD
equal to zero volts, the
UT54ACS164245S outputs and inputs present a minimum im-
pedance of 1MΩ making it ideal for "cold spare" applications.
Balanced outputs and low "on" output impedance make the
UT54ACS164245S well suited for driving high capacitance
loads and low impedance backplanes. The UT54ACS164245S
enables system designers to interface 3.3 volt CMOS compati-
ble components with 5 volt CMOS components. For voltage
translation, the A port interfaces with the 3.3 volt bus; the B
port interfaces with the 5 volt bus. The direction control (DIRx)
controls the direction of data flow. The output enable (OEx)
overrides the direction control and disables both ports. These
signals can be driven from either port A or B. The direction and
output enable controls operate these devices as either two inde-
pendent 8-bit transceivers or one 16-bit transceiver.
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
PIN DESCRIPTION
Pin Names
OEx
DIRx
xAx
xBx
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (3.3V Port)
Side B Inputs or 3-State Outputs (5V Port)
FUNCTION TABLE
ENABLE
OEx
L
L
H
DIRECTION
DIRx
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
1
PINOUTS
POWER TABLE
1
Port B
5 Volts
5 Volts
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port B Cold Spare
48-Lead Flatpack
Top View
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
OE2
3.3 Volts
V
SS
V
SS
NOTE:
1. V
DD2
cannot be tied to V
SS
while power is applied to V
DD1
.
Control signals DIRx and OEx are 5 volt tolerant inputs. When
V
DD2
is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can
be applied to all control inputs. For proper operation connect
power to all V
DD
and ground all V
SS
pins (i.e., no floating V
DD
or V
SS
input pins). Tie unused inputs to V
SS
. If V
DD1
and V
DD2
are not powered up together, then V
DD2
should be powered up
first for proper control of OE and DIR. Until V
DD2
reaches
2.75V + 5%, control of the outputs by OE and DIR cannot be
guaranteed. During operation of the part, after power up, insure
V
DD1
> V
DD2
. Tie unused inputs to V
SS
.
2
LOGIC DIAGRAM
DIR1
(1)
(48)
OE1
DIR2
(24)
(25)
OE2
1A1
(47)
(2)
1B1
2A1
(36)
(13)
2B1
1A2
(46)
(3)
1B2
2A2
(35)
(14)
2B2
1A3
(44)
(5)
1B3
2A3
(33)
(16)
2B3
3.3V PORT
3.3V PORT
1A4
(43)
2A4
(32)
(17)
2B4
5 V PORT
(6)
1A5
(41)
(8)
1A6
(40)
(9)
1A7
(38)
(11)
1A8
(37)
(12)
1B4
2A5
(30)
(19)
2B5
1B5
2A6
1B6
2A7
1B7
2A8
1B8
(26)
(27)
(29)
(20)
2B6
(22)
2B7
(23)
2B8
3
5 V PORT
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Latchup
Neutron Fluence
2
LIMIT
1.0E5
>120
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O
(Port B)
2
V
I/O
(Port A)
2
V
DD1
V
DD2
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin during operation
Voltage any pin during operation
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD1
+.3
-.3 to V
DD2
+.3
-0.3 to 6.0
-0.3 to 6.0
-65 to +150
+175
20
±10
1
V
V
°C
°C
°C/W
mA
W
UNITS
V
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (V
DD
= V
SS
), V
I/O
may be -0.3V to the maximum recommended operating V
DD
+ 0.3V.
DUAL SUPPLY OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
V
IN
(Port B)
V
IN
(Port A)
T
C
PARAMETER
Supply voltage
Supply voltage
Input voltage any pin
Input voltage any pin
Temperature range
LIMIT
3.0 to 3.6 or 4.5 to 5.5
3.0 to 3.6 or 4.5 to 5.5
0 to V
DD1
0 to V
DD2
-55 to + 125
UNITS
V
V
V
V
°C
4
DC ELECTRICAL CHARACTERISTICS
1
( -55°C < T
C
< +125°C)
(T
C
= -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)
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