X28C512/X28C513
512K
X28C512/X28C513
5 Volt, Byte Alterable E
2
PROM
64K x 8 Bit
FEATURES
•
•
•
•
•
•
•
•
Access Time: 90ns
Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 50mA
—Standby: 500µA
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
TSOP
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Two PLCC and LCC Pinouts
—X28C512
—X28C010 E
2
PROM Pin Compatible
—X28C513
—Compatible with Lower Density E
2
PROMs
DESCRIPTION
The X28C512/513 is an 64K x 8 E
2
PROM, fabricated
with Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C512/513 is a 5V only device.
The X28C512/513 features the JEDEC approved pinout
for bytewide memories, compatible with industry stan-
dard EPROMS.
The X28C512/513 supports a 128-byte page write op-
eration, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512/513 also features
DATA
Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512/513 supports the Software Data
Protection option.
PIN CONFIGURATIONS
PLCC / LCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
PLASTIC DIP
CERDIP
FLAT PACK
SOIC (R)
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28C512
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3856 FHD F01
X28C512
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
30
32 31 29
54 3 2
1
6
28
7
27
26
8
X28C512
25
9
(TOP VIEW)
24
10
11
23
12
22
13
15 16 17 18 19 20 21
14
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
A12
A15
NC
NC
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
3856 FHD F03
PGA
I/O0
I/O2
I/O3
I/O5
I/O6
15
17
19
21
22
A1
13
A2
12
A4
10
A6
8
A12
6
A0
14
A3
11
A5
9
A7
7
A15
5
NC
4
NC
2
NC
3
VCC
NC
36
34
NC
1
WE
35
BOTTOM
VIEW
CE
I/O1
VSS
I/O4
I/O7
16
18
20
23
24
A10
25
A11
27
A8
29
NC
32
NC
33
OE
26
A9
28
A13
30
A14
31
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
30
32 31 29
54 3 2
1
6
28
7
27
26
8
X28C513
25
9
(TOP VIEW)
24
10
11
23
12
22
13
15 16 17 18 19 20 21
14
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
A7
A12
A14
A15
VCC
WE
A13
3856 ILL F22
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
3856 FHD F02
3856 FHD F04
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3856-3.1 2/24/99 T1/C0/D0 NS
1
Characteristics subject to change without notice
X28C512/X28C513
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X28C512/513 supports both
a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either
CE
or
WE,
which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28C512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28C512/513 prior to the
commencement of the internal programming cycle. The
host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A
7
through A
15
) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE
HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding
WE.
If a subsequent
WE
HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28C512/513 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3856 FHD F06
DATA
Polling (I/O
7
)
The X28C512/513 features
DATA
Polling as a method
to indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the X28C512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28C512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28C512/X28C513
The Toggle Bit I/O
6
Figure 3a. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
I/O6
VOH
*
VOL
HIGH Z
*
X28C512/513
READY
3856 FHD F09.1
* Beginning and ending state of I/O6 will vary.
Figure 3b. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement
DATA
Polling.
This can be especially helpful in an array comprised of
multiple X28C512/513 memories that is frequently up-
dated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C512
READY
NO
3856 FHD F10
5
FPGA/CPLD
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