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5962F9653901QXX

Description
XOR Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14
Categorylogic    logic   
File Size224KB,9 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962F9653901QXX Overview

XOR Gate, ACT Series, 4-Func, 2-Input, CMOS, CDFP14, CERAMIC, BOTTOM BRAZED, DFP-14

5962F9653901QXX Parametric

Parameter NameAttribute value
package instructionDFP,
Reach Compliance Codeunknown
seriesACT
JESD-30 codeR-CDFP-F14
Logic integrated circuit typeXOR GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)14 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose300k Rad(Si) V
width6.2865 mm
Base Number Matches1
Standard Products
UT54ACS86/UT54ACTS86
Quadruple 2-Input Exclusive OR Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS86 - SMD 5962-96538
UT54ACTS86 - SMD 5962-96539
DESCRIPTION
The UT54ACS86 and the UT54ACTS86 are quadruple 2-input
exclusive OR gates. The devices perform the Boolean function
Y = A⊕B = AB + AB in positive logic.
An application is as a true/complement element. If one of the
inputs is low, the other input will be reproduced in true form at
the output. If one of the inputs is high, the signal on the other
input will be reproduced inverted at the output.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
L
L
H
H
B
L
H
L
H
OUTPUT
Y
L
H
H
L
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
=1
(3)
(6)
(8)
(11)
Y1
Y2
Y3
Y4
Y1
Y2
Y3
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
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