FD5T Series
FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
• Pletronics’ FD51T Series is a quartz crystal
controlled precision square wave generator
• Output frequency 32.768KHz
• Selectable low jitter or spread spectrum output.
• Device characteristics may be either factory or
field programmable
• Tape and Reel or cut tape packaging is available
•
Vdd 1.8V (5)
Vddout
(6)
Reference
oscillator
optional
Voltage
controlled
• 3.2 x 5 mm LCC Ceramic Package
• Stability is much better than
an XY cut watch crystal
• Very fast Start-up time, <10mS
• Low power
• 1.8V, 2.5 or 3.3V LVCMOS outputs
• Designed for high density SMD needs
Optional
Vcontrol
S2/SCL (1)
S1/SDA (2)
Ground (3)
PLL Multiplier #1
optional
Spread Spectrum
optional
Bypass Mode
MUX #1
Divider #1
/1 to /1023
Y1
(4)
Out
- Programming
control
- eePROM
- SDA/SCL
Registers
- Sx Control
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.09 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
DD
V
DDOUT
Vi
Vo
Io
Input Voltage
Output Voltage
Continuous Output Current
Unit
-0.5V to +2.5V
-0.5V to +4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDOUT
+ 0.5V
_ 50 mA
+
125
o
C
50
o
C/Watt
Tj Maximum Junction Temperature
Thermal Resistance, Junction to Case
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2009, Pletronics Inc.
FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Description:
The FD51xxT-32.768K is derived from the PLE FD51T series Programmable CMOS Clock Oscillator
which is a modular PLL-based low cost, high-performance oscillator. The frequency output is set to
32.768KHz. The FD51xxT-32.768K base frequency is a 24.576MHz AT cut fundamental mode crystal.
The FD5T has a separate output supply pin, V
DDOUT
, for either 1.8, 2.5 or 3.3V output logic levels. The
device supply, V
DD
which provides power to all the internal circuits, is nominally 1.8V.
The PLL is only utilized to support Spread Spectrum Clocking (SSC), in all other cases the PLL is disabled
to reduce power. SSC may be programmed to be either center-spread or down-spread. This is an
important technique to reduce electro-magnetic interference (EMI).
The device supports non-volatile eePROM programming for easy customization of the device. As
shipped, the device is pre-programmed. However, the FD51xxT-32.768K may be reprogrammed to a
different configuration. Reprogramming may be either prior to assembly, or in-circuit via a 2-wire
SDA/SCL I
2
C bus. In-circuit programming is not allowed if the VCXO function is needed.
Two programmable control inputs, S1 and S2, may be used to control various aspects of
FD51xxT-32.768K operation including selection of alternative frequency set(s), selection of SSC
functionality, output tri-state and power-down.
Reference Oscillator
The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A
resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range
that changes the frequency will still be limited but the larger voltages swings will not cause problems.
The VCXO function is only enabled (internally connected) if the part number indicates a VCXO
specification. When the VCXO function is enabled the I
2
C programming mode will be disabled.
PLL Multiplier
The PLL Multiplier is enabled when tight tolerances are needed or when the spread spectrum function is
needed.
Spread Spectrum
The PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the
modulation of the output frequency by a user-set amount.
Divider Section
The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 1023 and
is set to 750 in this case. There is only 1 setting allowed per divider. These are not set by the Sx input
state.
The dividers add very little jitter to the output signals.
Multiplexers
MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from
www.pletronics.com
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
PLL Multiplier #1.
The device can make only one of the setting of connections shown in the block diagram (only one
pattern stored in eePROM).
Control Inputs
The two inputs, S1/SDA and S2/SCL can be configured in two ways.
1) Used as 2 user inputs to permit up to 4 states, Sx input setting.
2) The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.
The interface follows the I
2
C protocol. If the SDA and SCL are not set then the internal eePROM
sets the operation. (Not allowed if the VCXO function is specified.)
Standard Configuration
S1
Low
High
Low
High
S2
Low
Low
High
High
Output
Tri State
32.768KHz
32.768KHz
32.768KHz
SS
---
±1% centered
±2% centered
none
PLL
Disable
Enable
Enable
Disable
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
PART NUMBER:
FD5 1 45 T L E -32.768K -YYY
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Output Frequency - 32.768KHz
Optional Enhanced Operating temperature Range
Blank
= Temp. range -20
o
C to +70
o
C
E
= Temp. range -40
o
C to +85
o
C
Blank
= V
DDOUT
3.3V, 2.5V and 1.8V device
L
= V
DDOUT
1.8V only - high output drive level device
Series Model
Frequency Stability for fixed frequency oscillator
45
= + 50 ppm
_
15
= + 15 ppm
1
_
44
= _ 25 ppm
+
10
= + 10 ppm
1
_
20
= _ 20 ppm
+
Frequency Pull Ability for VCXO option enabled
99
= _ 100 ppm Absolute Pull Range (APR)
+
75
= _ 25 ppm Absolute Pull Range (APR)
+
50
= _ 50 ppm Absolute Pull Range (APR)
+
1
= 1 output
Series Model
1
1 PLL version
In these cases the PLL will be enabled and the power dissipation will be higher.
Part Marking:
PLE FD51
32.768K
YMD
PLE = Pletronics
YMD
=
Date of Manufacture (year-month-day)
All other marking is internal factory codes
Marking Legend:
Codes for Date Code YMD
Code
Code
A
8
9
0
1
2
B
C
D
E
F
G
H
J
K
L
M
Year
2008 2009 2010 2011 2012
Month
JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC
Code
Day
Code
Day
1
1
H
17
2
2
J
18
3
3
K
19
4
4
L
20
5
5
M
21
6
6
N
22
7
7
P
23
8
8
R
24
9
9
T
25
A
10
U
26
B
11
V
27
C
12
W
28
D
13
X
29
E
14
Y
30
F
15
Z
31
G
16
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FD51xxT-32.768KHz
CMOS Clock Oscillator
March 2009
Electrical Specification over the specified temperature range
,
Item
Frequency Accuracy
“45"
“44"
“20"
“15"
“10"
Start-up Time
Recommended Operating Conditions
Device Supply Voltage V
DD
Output Supply Voltage V
DDOUT
Output Supply Voltage “L” V
DDOUT
Low Level Input voltage
High Level Input voltage
Input Voltage Range, S1, S2
Input current for: S1, S2
1.7
1.7
1.7
--
70
0
0
-4
Output Current, V
DDOUT
= 3.3V
Output Current, V
DDOUT
= 2.5V
Output Current, V
DDOUT
= 1.8V
Output Current “L”, V
DDOUT
= 1.8V
Output Load, LVCMOS
-12
-10
-5
-8
--
1.9
3.6
1.9
30
--
3.6
5
0
+12
+10
+5
+8
10
V
V
V
%
%
V
µA
µA
mA
mA
mA
mA
pf
Higher loads can be used
of V
DD
of V
DD
V
TH
is 0.5 * V
DD
V
IN
= V
DD
; V
DD
= 1.9V
V
IN
= 0.0V
D
; V
DD
= 1.9V
Min
-50
-25
-20
-15
-10
--
Max
+50
+25
+20
+15
+10
10
mS
Unit
ppm
Condition
For all supply voltages, load changes,
aging for 1 year, shock, vibration and
temperatures
LVCMOS Output Parameters for V
DDOUT
= 3.3v
Output High, V
DDOUT
= 3.3V
2.9
2.4
2.2
Output Low, V
DDOUT
= 3.3V
--
--
--
Rise & Fall Time
I
DD
I
DD
I
DDOUT
Output Symmetry
Peak-to-Peak Jitter
(1)
(no PLL enabled)
(PLL enabled)
--
--
--
--
45
--
--
--
--
0.1
0.5
0.8
0.6
2.5
9
5
55
10
V
V
V
V
V
V
nS
mA
mA
uA
%
pS
SS option or 15ppm or 10 ppm stability
10pF Load
at 50% point of V
DDOUT
(No SS and PLL disabled)
I
OH
= -0.1 mA
I
OH
= -8.0 mA
I
OH
= -12.0 mA
I
OH
= +0.1 mA
I
OH
= +8.0 mA
I
OH
= +12.0 mA
V
DDOUT
= 3.3v, 20 - 80%, 10pF Load
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