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5962R9655602VXC

Description
Serial In Parallel Out, AC Series, 8-Bit, Right Direction, True Output, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14
Categorylogic    logic   
File Size202KB,10 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962R9655602VXC Overview

Serial In Parallel Out, AC Series, 8-Bit, Right Direction, True Output, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14

5962R9655602VXC Parametric

Parameter NameAttribute value
package instructionDFP,
Reach Compliance Codeunknown
Counting directionRIGHT
seriesAC
JESD-30 codeR-CDFP-F14
JESD-609 codee4
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Number of digits8
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)25 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.6 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose100k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.2865 mm
Base Number Matches1
UT54ACS164E/UT54ACTS164E
Radiation-Hardened
8-Bit Shift Registers
FEATURES
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
0.6µm
CRH CMOS Process
- Latchup immune
High speed
Low power consumption
Wide operating power supply from 3.0V to 5.5V
Available QML Q or V processes
Flexible package
- 14-lead flatpack
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
A
X
X
H
L
X
B
X
X
H
X
L
Q
A
L
Q
A0
H
L
L
OUTPUTS
Q
B
L
Q
B0
Q
An
Q
An
Q
An
...
Q
H
L
Q
H0
Q
Gn
Q
Gn
Q
Gn
DESCRIPTION
The UT54ACS164E and the UT54ACTS164E are 8-bit shift
registers which feature AND-gated serial inputs and an asyn-
chronous clear. The gated serial inputs (A and B) permit com-
plete control over incoming data. A low at either input inhibits
entry of new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level at both serial inputs sets
the first flip-flop to the high level at the next clock pulse. Data
at the serial inputs may be changed while the clock is high or
low, providing the minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition of the clock
input.
The devices are characterized over full military temperature
range of -55°C to +125°C.
Notes:
1. Q
A0
, Q
B0
, Q
H0
= the level of Q
A
, Q
B
or Q
H
, respectively, before the indicated
steady-state input conditions were established.
2. Q
An
and Q
Gn
= the level of Q
A
or Q
G
before the most recent
transition of
the clock; indicates a one-bit shift.
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A
(1)
(2)
SRG8
R
C1/
&
1D
(3)
(4)
PINOUT
14-Lead Flatpack
Top View
A
B
Q
A
Q
B
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
B
Q
A
Q
B
(5)
Q
(6)
C
Q
D
(10)
Q
(11)
E
Q
(12)
F
Q
(13)
G
Q
H
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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