Three-state outputs drive bus lines or buffer memory address
registers
• 0.6µm
CRH CMOS Process
- Latchup immune
•
High speed
•
Low power consumption
•
Wide operating power supply from 3.0V to 5.5V
•
Available QML Q or V processes
•
20-lead flatpack
DESCRIPTION
The UT54ACTS541E is a non-inverting octal buffer and line
driver which improves the performance and density of three-
state memory address drivers, clock drivers, and bus-oriented
receivers and transmitters.
The device is characterized over full military temperature range
of -55°C to +125°C.
PINOUT
20-Lead Flatpack
Top View
1G
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
2G
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
FUNCTION TABLE
INPUTS
1G
L
L
H
X
2G
L
L
X
H
An
L
H
X
X
OUTPUT
Yn
L
H
Z
Z
LOGIC SYMBOL
1G
2G
(1)
(19)
&
EN
A1 (2)
(3)
A2
A3 (4)
(5)
A4
A5 (6)
A6 (7)
A7 (8)
A8 (9)
(18)
Y1
(17)
Y2
(16) Y3
(15)
(14)
(13)
(12)
(11)
Y4
Y5
Y6
Y7
Y8
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
LOGIC DIAGRAM
A8
(9)
A7
(8)
A6
(7)
A5
(6)
A4
(5)
A3
(4)
A2
(3)
A1
2G 1G
(1)
(2) (19)
(11)
Y8
(12)
Y7
(13)
Y6
(14)
Y5
(15)
Y4
(16)
Y3
(17)
Y2
(18)
Y1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
2
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to +125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS541E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
Description
Low-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
V
IN
= V
DD
or V
SS
I
OL
= 8mA
I
OL
= 12mA
V
OH
High-level output voltage
3
I
OH
= -8mA
I
OH
= -12mA
I
OS
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS
CONDITION
VDD
3.0V
5.5V
V
IH
3.0V
5.5V
I
IN
V
OL
5.5V
3.0V
4.5V
3.0V
4.5V
3.0V
5.5V
I
OL
Low level output current
10
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
I
OH
High level output current
10
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
P
total
I
DDQ
∆I
DDQ
Power dissipation
2, 8 ,9
Quiescent Supply Current
Quiescent Supply Current Delta
C
L
= 50pF
V
IN
= V
DD
or V
SS
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz
ƒ
= 1MHz
0V
0V
15
15
pF
pF
3.0V
5.5V
3.0V
5.5V
5.5V
3.0V
5.5V
5.5V
2.4
3.15
-150
-300
8
12
-8
-12
2.1
0.84
10
1.6
mW/
MHz
µA
mA
mA
150
300
mA
2.0
2.75
-1
1
0.4
0.4
µA
V
V
V
V
mA
MIN
MAX
0.8
0.8
V
UNIT
V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B.
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
4
10. This value is guaranteed based on characterization data, but not tested.
京公网安备 11010802033920号
EEWORLD
