BUK95/9608-55A
TrenchMOS™ logic level FET
Rev. 03 — 6 May 2002
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9508-55A in SOT78 (TO-220AB)
BUK9608-55A in SOT404 (D
2
-PAK).
2. Features
s
s
s
s
TrenchMOS™ technology
Q101 compliant
175
°C
rated
Logic level compatible.
3. Applications
s
Automotive and general purpose power switching:
x
12 V and 24 V loads
x
Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pin
1
2
3
mb
Pinning - SOT78 and SOT404, simplified outline and symbol
Description
gate (g)
mb
Simplified outline
mb
Symbol
d
drain (d)
source (s)
mounting base;
connected to drain (d)
[1]
g
s
MBB076
2
1
MBK106
3
MBK116
1 2 3
SOT78 (TO-220AB)
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
SOT404 (D
2
-PAK)
Philips Semiconductors
BUK95/9608-55A
TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
T
mb
= 25
°C;
V
GS
= 5 V
T
mb
= 25
°C
T
j
= 25
°C;
V
GS
= 5 V; I
D
= 25 A
T
j
= 25
°C;
V
GS
= 4.5 V; I
D
= 25 A
T
j
= 25
°C;
V
GS
= 10 V; I
D
= 25 A
Typ
-
-
-
-
6.8
-
6.4
Max
55
125
253
175
8
8.5
7.5
Unit
V
A
W
°C
mΩ
mΩ
mΩ
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
6. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
T
mb
= 25
°C;
V
GS
= 5 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V;
Figure 2
I
DM
P
tot
T
stg
T
j
I
DR
I
DRM
peak drain current
total power dissipation
storage temperature
junction temperature
reverse drain current (DC)
peak reverse drain current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 75 A;
V
DS
≤
55 V; V
GS
= 5 V; R
GS
= 50
Ω;
starting T
mb
= 25
°C
[1]
[2]
[1]
[2]
[2]
Conditions
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
-
−55
−55
-
-
-
-
Max
55
55
±15
125
75
75
503
253
+175
+175
125
75
503
670
Unit
V
V
V
A
A
A
A
W
°C
°C
A
A
A
mJ
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source avalanche
energy
[1]
[2]
Current is limited by power dissipation chip rating
Continuous current is limited by package.
9397 750 09573
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 6 May 2002
2 of 14
Philips Semiconductors
BUK95/9608-55A
TrenchMOS™ logic level FET
120
Pder
(%)
80
03na19
150
ID
(A)
03ni52
100
40
50
Capped at 75 A due to package
0
0
50
100
150
200
Tmb
(°C)
0
25
50
75
100
125
150
175
200
Tmb (ºC)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
V
GS
≥
4.5 V
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
103
03ni50
ID
(A)
Limit RDSon = VDS/ID
tp = 10 µs
102
100 µs
Capped at 75 A due to package
1 ms
10
DC
10 ms
100 ms
1
10-1
1
10
VDS (V)
102
T
mb
= 25
°C;
I
DM
single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09573
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 6 May 2002
3 of 14
Philips Semiconductors
BUK95/9608-55A
TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
Min
-
Typ
-
Max
0.59
Unit
K/W
thermal resistance from junction to
mounting base
thermal resistance from junction to ambient
SOT78
SOT404
vertical in still air
mounted on a printed circuit board;
minimum footprint
-
-
60
50
-
-
K/W
K/W
Symbol Parameter
7.1 Transient thermal impedance
1
Zth(j-mb)
(K/W)
δ
= 0.5
03ni51
0.2
10-1
0.1
0.05
0.02
10-2
P
δ
=
tp
T
single shot
tp
t
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09573
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 6 May 2002
4 of 14
Philips Semiconductors
BUK95/9608-55A
TrenchMOS™ logic level FET
8. Characteristics
Table 5:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol
V
(BR)DSS
Parameter
drain-source breakdown
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 55 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state
resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 4.5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
d
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
from drain lead 6 mm from
package to centre of die
from contact screw on
mounting base to centre of
die SOT78
from upper edge of drain
mounting base to centre of
die SOT404
L
s
internal source inductance
from source lead to source
bond pad
V
DD
= 30 V; R
L
= 1.2
Ω;
V
GS
= 5 V; R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
V
GS
= 5 V; V
DD
= 44 V;
I
D
= 25 A;
Figure 14
-
-
-
-
-
-
-
-
-
-
-
-
92
11
43
4551
760
500
40
175
280
167
4.5
3.5
-
-
-
6021
900
687
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
-
-
-
-
6.8
-
-
6.4
8
16
8.5
7.5
mΩ
mΩ
mΩ
mΩ
-
-
-
0.05
-
2
10
500
100
µA
µA
nA
1
0.5
-
1.5
-
-
2
-
2.3
V
V
V
55
50
-
-
-
-
V
V
Min
Typ
Max
Unit
Static characteristics
-
2.5
-
nH
-
7.5
-
nH
9397 750 09573
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 03 — 6 May 2002
5 of 14
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