DATA SHEET
256M bits SDRAM
EDS2532CASG (8M words
×
32 bits)
Specifications
•
Density: 256M bits
•
Organization
⎯
2M words
×
32 bits
×
4 banks
•
Package: 90-ball FBGA
⎯
Lead-free (RoHS compliant)
•
Power supply: VDD, VDDQ
=
2.5V
±
0.2V
•
Clock frequency: 133MHz/100MHz (max.)
•
2KB page size
⎯
Row address: A0 to A11
⎯
Column address: A0 to A8
•
Four internal banks for concurrent operation
•
Interface: LVTTL
•
Burst lengths (BL): 1, 2, 4, 8, full page
•
Burst type (BT):
⎯
Sequential (1, 2, 4, 8, full page)
⎯
Interleave (1, 2, 4, 8)
•
/CAS Latency (CL): 2, 3
•
Precharge: auto precharge operation for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 4096 cycles/64ms
⎯
Average refresh period: 15.6μs
•
Operating ambient temperature range
⎯
TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
1
2
3
4
5
6
7
A
DQ13 VSS
VDD
VSS
VDD
DQ2
DQ4
DQ3
DQ6
VDD
EO
Features
B
DQ11 DQ15 VSSQ
VDDQ DQ0
VSSQ DQ1
VDDQ DQ5
VSSQ DQ7
VSS
/CS
NC
BA1
A1
C
DQ14 DQ12 VDDQ
D
DQ10 DQ9 VSSQ
E
DQ8
VDD VDDQ
F
VSS DQM1 VDD
/WE DQM0
/CAS /RAS
A11
A10
A2
BA0
A0
DQM2
• ×32
organization
•
Single pulsed /RAS
•
Burst read/write operation and burst read/single write
operation capability
•
Byte control by DQM
Document No. E0541E21 (Ver. 2.1)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2004-2006
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CLK
CKE
A8
A5
A9
A7
A4
H
NC
J
A6
K
A3
DQM3 VDD
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Pr
L
VSS DQ31 VDDQ
VSSQ DQ16 VSS
M
N
P
DQ29 DQ30 VSSQ
VDDQ DQ17 DQ18
VSSQ DQ22 DQ20
DQ25 DQ27 VDDQ
DQ28 DQ24 VSSQ
DQ26 VSS
VDD
VDDQ DQ23 DQ19
VSS
VDD DQ21
R
(Top view)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
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EDS2532CASG
Ordering Information
Part number
EDS2532CASG-75-E
EDS2532CASG-1A-E
Supply
voltage
2.5V
Organization
(words
×
bits) Internal Banks
8M
×
32
4
Clock frequency
MHz (max.)
133
100
100
/CAS latency
3
2
2, 3
Package
90-ball FBGA
Part Number
E D S 25 32 C A SG - 75 - E
Elpida Memory
EO
Type
D: Monolithic Device
Product Code
S: SDRAM
Environment Code
E: Lead Free
Speed
75: 133MHz/CL3
100MHz/CL2
1A: 100MHz/CL2,CL3
Package
SG: FBGA
Density / Bank
25: 256M/4-bank, 4K Rows
Bit Organization
32: x32
Voltage, Interface
C: 2.5V, LVTTL
Die Rev.
Data Sheet E0541E21 (Ver. 2.1)
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EDS2532CASG
CONTENTS
Specifications ................................................................................................................................................ 1
Features ........................................................................................................................................................ 1
Pin Configurations......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Part Number.................................................................................................................................................. 2
Electrical Specifications ................................................................................................................................ 4
Block Diagram............................................................................................................................................... 9
Pin Function ................................................................................................................................................ 10
Command Operation................................................................................................................................... 11
Simplified State Diagram ............................................................................................................................ 19
Mode Register Configuration ...................................................................................................................... 20
Power-up sequence .................................................................................................................................... 22
Operation of the SDRAM ............................................................................................................................ 23
Timing Waveforms ...................................................................................................................................... 39
Package Drawing........................................................................................................................................ 45
Recommended Soldering Conditions ......................................................................................................... 46
EO
Data Sheet E0541E21 (Ver. 2.1)
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EDS2532CASG
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–0.5 to +3.6
–0.5 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
EO
Storage temperature
Parameter
Supply voltage
Input high voltage
Input low voltage
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol
VDD, VDDQ
min.
2.3
0
1.7
–0.3
max.
2.7
0
VDD + 0.3
0.7
Unit
V
V
V
V
Notes
1
2
3
4
L
VSS, VSSQ
VIH
VIL
Notes: 1.
2.
3.
4.
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width
≤
5ns).
VIL (min.) = VSS – 1.5V (pulse width
≤
5ns).
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Data Sheet E0541E21 (Ver. 2.1)
EDS2532CASG
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
power down (input signal stable)
Burst operating current
Refresh current
Symbol
IDD1
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4
IDD5
-75
-1A
-75
-1A
Grade
max.
125
3
2
20
9
4
3
50
30
155
125
265
255
3
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
tRC = tRC (min.)
VIH
≥
VDD – 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
EO
Self refresh current
Data Sheet E0541E21 (Ver. 2.1)
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
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