68634-413 datasheet, PDF - EEWORLD Datasheet

68634-413: DescriptionBoard Connector, 13 Contact(s), 1 Row(s), Male, Straight, Solder Terminal; CategoryThe connector The connector; File Size722KB，8 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

68634-413 Overview

Board Connector, 13 Contact(s), 1 Row(s), Male, Straight, Solder Terminal

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Amphenol
Reach Compliance Code	compli
Other features	BERGSTRIP
Connector type	BOARD CONNECTOR
Contact to complete cooperation	TIN (100) OVER NICKEL (50)
Contact completed and terminated	TIN (100) OVER NICKEL (50)
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
DIN compliance	NO
Filter function	NO
IEC compliance	NO
JESD-609 code	e3
MIL compliance	NO
Manufacturer's serial number	68634
Mixed contacts	NO
Installation method	STRAIGHT
Installation type	BOARD
Number of rows loaded	1
Options	GENERAL PURPOSE
Terminal pitch	2.54 mm
Termination type	SOLDER
Total number of contacts	13
UL Flammability Code	94V-0

PDM: Rev:CW

STATUS:

Released

Printed: Oct 15, 2010

Initialization of string pointers: If you want to initialize a string, there are two ways to write it: 1: char *p = "hello"; 2: char *p; p = "hello"; Are these two ways wrong? Are there any differences? Tan Haoqiang C Programming p238 ...; louis0711 Embedded System

Zigbeez: How many companies have mature solutions in smart home?: I want to build a smart home system using Zigbee technology. Are there many manufacturers like this? Which ones are good at it?...; sciencefor RF/Wirelessly

Help with FPGA and 2812 communication issues: I need help with the communication problem between two controllers. Explanation: Use XINTF for communication, FPGA sends 16-bit numbers to dsp data bus, dsp reads the data on the data bus through peri...; leejian113 FPGA/CPLD

Verilog problem with keypress: module key(clk,key_in,key_out); input clk; input[3:0]key_in;//key inputoutput[3:0]key_out; reg[3:0]dout1,dout2,dout3; reg[3:0]a; reg i; //assign key_out=a; always@(posedge clk)//key debounce begin dou...; hjl240 FPGA/CPLD

The task scheduling cycle of DM8168 is problematic. The simplest task will also intermittently have a scheduling cycle of about 335ms.: After the DM8168 system is started, only one main task is created, and only the following simple loop is performed in it, which is to continuously print the current execution time interval. Statistics...; yelo DSP and ARM Processors

I don't know if it's a hardware bug of stm32vet6Z: When USART3 is mapped in mode 2 (mapped to PD8, PD9), the AFIO function must be enabled first, and then the related peripherals must be initialized before USART is effective.The following code is corr...; mary1127 stm32/stm8

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components