PRELIMINARY DATA SHEET
256M bits DDR2 SDRAM
EDE2504AASE (64M words
×
4 bits)
EDE2508AASE (32M words
×
8 bits)
EDE2516AASE (16M words
×
16 bits)
Description
The EDE2504AA is a 256M bits DDR2 SDRAM
organized as 16,777,216 words
×
4 bits
×
4 banks.
The EDE2508AA is a 256M bits DDR2 SDRAM
organized as 8,388,608 words
×
8 bits
×
4 banks.
They are packaged in 64-ball FBGA package.
The EDE2516AA is a 256M bits DDR2 SDRAM
organized as 4,194,304 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA package.
Features
•
1.8V power supply
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
•
Four internal banks for concurrent operation
•
Data mask (DM) for write data
•
Burst lengths: 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Auto precharge operation for each burst access
•
Auto refresh and self refresh modes
•
7.8µs average periodic refresh interval
•
1.8V (SSTL_18 compatible) I/O
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
•
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
•
FBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0427E11 (Ver. 1.1)
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003-2006
EDE2504AASE, EDE2508AASE, EDE2516AASE
Ordering Information
Part number
EDE2504AASE-6E-E
EDE2504AASE-5C-E
EDE2504AASE-4A-E
EDE2504AASE-4C-E
EDE2508AASE-6E-E
EDE2508AASE-5C-E
EDE2508AASE-4A-E
EDE2508AASE-4C-E
EDE2516AASE-6E-E
EDE2516AASE-5C-E
EDE2516AASE-4A-E
EDE2516AASE-4C-E
Mask
version
Organization
(words
×
bits)
64M
×
4
Internal
Banks
Speed bin
(CL-tRCD-tRP)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
Package
A
4
64-ball FBGA
32M
×
8
16M
×
16
84-ball FBGA
Part Number
E D E 25 04 A A SE - 5C - E
Elpida Memory
Type
D: Monolithic Device
Product Code
E: DDR2
Environment code
Blank: Sn-Pb solder
E: Lead Free
Density / Bank
25: 256Mb /4-bank
Bit Organization
04: x4
08: x8
16: x16
Voltage, Interface
A: 1.8V, SSTL_18
Speed
6E: DDR2-667 (5-5-5)
5C: DDR2-533 (4-4-4)
4A: DDR2-400 (3-3-3)
4C: DDR2-400 (4-4-4)
Package
SE: FBGA (with back cover)
Die Rev.
Preliminary Data Sheet E0427E11 (Ver. 1.1)
2
EDE2504AASE, EDE2508AASE, EDE2516AASE
Pin Configurations
/xxx indicates active low signal.
64-ball FBGA
(×8,
×4
organization)
1
A
NC
B
C
D
E
VDD
NU/ /RDQS
VSS
(NC)*
84-ball FBGA
(×16 organization)
8
NC
9
NC
A
VDD
B
DQ14 VSSQ UDM
C
VDDQ
D
E
DQ9 VDDQ
VDDQ
DQ8
VDDQ
UDQS VSSQ DQ15
NC
VSS
VSSQ /UDQS VDDQ
1
2
3
7
8
9
2
NC
3
7
DQ12 VSSQ DQ11
VDD
NC
VSSQ
VSS
LDM
DQ10 VSSQ DQ13
VSSQ /LDQS VDDQ
LDQS VSSQ
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
NC
VSS
VDD
DQ7
VDDQ
DQ5
VDD
ODT
VSSQ /DQS VDDQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
(Top view)
VSSQ
DQ0
VSSQ
CK
/CK
/CS
M
A0
A4
P
A8
NC
VSS
R
VDD
N
(NC)*
F
G
DQ6
DM/RDQS
(NC)*
VSSQ
(DM)*
DQ7
F
DQ6
G
VDDQ
H
DQ4
J
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
VDDQ
H
J
(NC)*
DQ1 VDDQ
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
VDDQ
(NC)*
DQ1 VDDQ
DQ4
DQ5
VDDL VREF
K
CKE
L
NC
M
A10
N
VSS
P
A7
R
VDD
A12
A3
BA0
VDD
K
ODT
L
VDDL VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
(Top view)
Note: ( )* marked pins are for
×4
organization.
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, /DQS
UDQS, /UDQS
LDQS, /LDQS
RDQS, /RDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM, UDM, LDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Differential data strobe for read
Chip select
Command input
Clock enable
Differential clock input
Write data mask
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*
NU*
1
2
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Preliminary Data Sheet E0427E11 (Ver. 1.1)
3
EDE2504AASE, EDE2508AASE, EDE2516AASE
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................15
Pin Function.................................................................................................................................................16
Command Operation ...................................................................................................................................18
Simplified State Diagram .............................................................................................................................25
Operation of DDR2 SDRAM ........................................................................................................................26
Package Drawing ........................................................................................................................................62
Recommended Soldering Conditions..........................................................................................................64
Preliminary Data Sheet E0427E11 (Ver. 1.1)
4
EDE2504AASE, EDE2508AASE, EDE2516AASE
Electrical Specifications
•
All voltages are referenced to VSS (GND)
•
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage for output
Power supply voltage for DLL
Input voltage
Output voltage
Storage temperature
Power dissipation
Short circuit output current
Symbol
VDD
VDDQ
VDDL
VIN
VOUT
Tstg
PD
IOUT
Rating
−1.0
to
+2.3
−0.5
to
+2.3
−0.5
to
+2.3
−0.5
to
+2.3
−0.5
to
+2.3
−55
to
+100
1.0
50
Unit
V
V
V
V
V
°C
W
mA
Note
1
1
1
1
1
1, 2
1
1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter
Operating case temperature
Symbol
TC
Rating
0 to
+85
Unit
°C
Note
1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. The operation temperature range is the temperature where all DRAM specification will be supported. Out
side of this temperature range, even it is still within the limit of stress condition, some deviation on portion
of operation specification may be required.
During operation, the DRAM case temperature must be maintained between 0 to +85°C under all other
specification parameters.
Preliminary Data Sheet E0427E11 (Ver. 1.1)
5
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