PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
Description
The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic
random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank),
respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
•
Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
•
Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
•
Quad internal banks operation
•
Possible to assert random column address in every clock cycle
•
Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
•
Automatic precharge and controlled precharge
•
CBR (Auto) refresh and self refresh
•
x4, x8, x16 organization
•
Byte write control (x4, x8) by DM
•
Byte write control (x16) by LDM and UDM
•
2.5 V
±
0.2 V Power supply for V
DD
•
2.5 V
±
0.2 V Power supply for V
DD
Q
•
Maximum clock frequency up to 133 MHz
•
SSTL_2 compatible with all signals
•
4,096 refresh cycles/64 ms
•
66-pin Plastic TSOP (II) (10.16 mm (400))
•
Burst termination by Precharge command and Burst stop command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0136E30 (Ver. 3.0)
Date Published October 2001 (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Pin Configurations
/xxx indicates active low signal.
[
EDD1204ALTA
]
66-pin Plastic TSOP (II) (10.16 mm (400))
8M word x 4 bit x 4 bank
V
DD
NC
V
DD
Q
NC
DQ0
V
SS
Q
NC
NC
V
DD
Q
NC
DQ1
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
NC
V
REF
V
SS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
A0 - A11
A0 - A11
BA0, BA1
DQ0 - DQ3
DQS
CLK, /CLK
CKE
/CS
/RAS
: Address inputs
: Row address inputs
: Bank select
: Data inputs/outputs
: Data strobe
: System clock input
: Clock enable
: Chip select
: Row address strobe
/CAS
/WE
DM
V
DD
V
SS
V
DD
Q
V
SS
Q
V
REF
NC
: Column address strobe
: Write enable
: DQ write mask enable
: Supply voltage
: Ground
: Supply voltage for DQ and DQS
: Ground for DQ and DQS
: Input reference
: No connection
A0 - A9, A11 : Column address inputs
4
Preliminary Data Sheet E0136E30
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