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5962-8984103LX

Description
FLASH PLD, 10 ns, CDIP24
CategoryProgrammable logic devices    Programmable logic   
File Size348KB,13 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

5962-8984103LX Overview

FLASH PLD, 10 ns, CDIP24

5962-8984103LX Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals24
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
Number of input and output buses10
Processing package description0.300 INCH, CERDIP-24
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeIN-LINE
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
terminal coatingTIN LEAD
Terminal locationDUAL
Packaging MaterialsCERAMIC, GLASS-SEALED
Temperature levelMILITARY
organize11 DEDICATED INPUTS, 10 I/O
Maximum FCLK clock frequency76.9 MHz
Output functionMACROCELL
Programmable logic typeFLASH PLD
propagation delay TPD10 ns
Dedicated input quantity11
PALCE22V10
is a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
PALCE22V10
Flash-erasable Reprogrammable
CMOS PAL
®
Device
Features
Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
• Variable product terms
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
— 5 ns commercial version
4 ns t
CO
3 ns t
S
5 ns t
PD
181-MHz state machine
— 10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-MHz state machine
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
• High reliability
— Proven Flash EPROM technology
— 100% programming and functional testing
Logic Block Diagram (PDIP/CDIP)
VSS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
I/O9
15
I/O8
16
I/O 7
17
I/O6
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
23
I/O0
24
V
CC
Pin Configuration
I
I
CP/I
NC
VCC
I/O0
I/O1
4 3 2 1 282726
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
12131415161718
V
SS
NC
I/O9
I/O8
I
I
I
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
I
I
CP/I
NC
V
CC
I/O0
I/O1
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
121314 1516 1718
V
SS
NC
I
I
I
LCC
Top View
PLCC
Top View
Cypress Semiconductor Corporation
Document #: 38-03027 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 9, 2004
I/O9
I/O8

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