PRELIMINARY DATA SHEET
4GB Fully Buffered DIMM
EBE41FE4ABHT
EBE41FE4ABHL
Specifications
•
Density: 4GB
•
Organization
512M words
×
72 bits, 2 ranks
•
Mounting 36 pieces of 1G bits DDR2 SDRAM with
sFBGA
•
Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
•
Power supply
DDR2 SDRAM: VDD
=
1.8V
±
0.1V
AMB: VCC
=
1.5V
+
0.075V/−0.045
•
Data rate: 667Mbps (max.)
•
Eight internal banks for concurrent operation
(components)
•
Interface: SSTL_18
•
Burst lengths (BL): 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Precharge: auto precharge option for each burst
access
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
TC = 0°C to +95°C
Features
•
JEDEC standard Raw Card D Design
•
Industry Standard Advanced Memory Buffer (AMB)
•
High-speed differential point-to-point link interface at
1.5V (JEDEC draft spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
•
Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
•
Channel error detection and reporting
•
Automatic DDR2 SDRAM bus and channel
calibration
•
SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
FB-DIMM
System clock
frequency
167MHz
Speed grade
PC2-5300F
Peak channel
throughput
8.0GByte/s
FB-DIMM link data rate
4.0Gbps
DDR2 SDRAM
Speed Grade
DDR2-667 (5-5-5)
DDR data rate
667Mbps
Document No. E1010E20 (Ver. 2.0)
Date Published January 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2006-2007
EBE41FE4ABHT, EBE41FE4ABHL
Ordering Information
Part number
EBE41FE4ABHT-6E-E
EBE41FE4ABHL-6E-E
DIMM speed
grade
PC2-5300F
PC2-5300F
Component JEDEC
speed bin (CL-tRCD-tRP)
DDR2-667 (5-5-5)
DDR2-667 (5-5-5)
Mounted devices*
1
Mounted AMB*
IDT Rev. C1
INTEL Rev. D1
2
1G bits DDR2 SDRAM
1G bits DDR2 SDRAM
Notes: 1. Please refer to 1Gb DDR2 datasheet (E0852E) for detailed operation part and timing waveforms.
2. Please refer to the following documents for detailed operation part and timing waveforms.
Advanced Memory Buffer (AMB) specification
FB-DIMM Architecture and Protocol specification
Part Number
E B E 41 F E 4 A B H T - 6E - E
Elpida Memory
Type
B: Module
Environment code
E: Lead Free
(RoHS compliant)
Product Family
E: DDR2
DRAM Speed Grade
6E: DDR2-667 (5-5-5)
Density / Rank
41: 4GB/2-rank
Module Type
F: Fully Buffered
Mono Density
E: 1Gbit
Mono Organization
4: x4
AMB Device Information
T: IDT, Rev.C1
L: Intel, Rev.D1
Module Outline
H: 240-pin DIMM
(Stacked FBGA)
Die Rev. (Mono)
Power Supply, Interface
A: 1.8V, SSTL_1.8
Preliminary Data Sheet E1010E20 (Ver. 2.0)
2
EBE41FE4ABHT, EBE41FE4ABHL
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol
Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large
memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing,
refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for
handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other
DIMMs on the FB-DIMM channel.
The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface.
FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is
288 devices per channel and total memory capacity scales with DRAM bit density.
The AMB is the buffer that isolates the DRAMs from the channel.
Advanced Memory Buffer Functionality
The AMB will perform the following FB-DIMM channel functions.
•
Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB
DIMM position.
•
Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames.
•
If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
•
Detects errors on the channel and reports them to the host memory controller.
•
Support the FB-DIMM configuration register set as defined in the register chapters.
•
Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM.
•
Provides a read buffer FIFO and a write buffer FIFO.
•
Supports an SMBus protocol interface for access to the AMB configuration registers.
•
Provides logic to support MemBIST and IBIST design for test functions.
•
Provides a register interface for the thermal sensor and status indicator.
•
Functions as a repeater to extend the maximum length of FB-DIMM links.
Preliminary Data Sheet E1010E20 (Ver. 2.0)
3
EBE41FE4ABHT, EBE41FE4ABHL
Advanced Memory Buffer Block Diagram
Southbound
10×2
Data in
10×2
Southbound
Data out
Reference
clock
1×2
PLL
Data merge
RE-time
Re-synch
Demux
PISO
/RESET
Reset
control
10×12
Thermal
sensor
failover
Command
decoder &
CRC check
Link init SM
and control
and CSRs
IBIST-RX
10×12
Init
patterns
Mux
4
IBIST-TX
DRAM clock
4
DRAM clock
Command
out
DRAM
interface
Data out
29
DRAM
address and
command copy1
DRAM
address and
command copy2
DRAM
data and strobes
LAI logic
DRAM Command
Mux
DDR state controller
and CSRs
29
Core
controller
and CSRs
Write data
FIFO
External MemBIST
DDR calibration
Sync & idle
pattern
generator
IBIST-TX
IBIST-RX
Mux
72+18×2
Data in
Data CRC
generator and
Read FIFO
LAI
controller
NB LAI Buffer
Mux
Link init SM
and control
and CSRs
SMBus
SMBus
controller
failover
14×6×2
PISO
14×12
Demux
Re-synch
RE-time
Data merge
Northbound 14×2
Data Out
14×2 Northbound
Data In
Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.
Preliminary Data Sheet E1010E20 (Ver. 2.0)
4
EBE41FE4ABHT, EBE41FE4ABHL
Interfaces
Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,
one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or
an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a FB-DIMM.
Memory Interface
NB FBD
out Link
SB FBD
in Link
AMB
NB FBD
in Link
SB FBD
out Link
SMB
Block Diagram AMB Interfaces
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8
DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven
to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the
next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the
direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives
the data to the next DIMM until the host is reached.
Host
Southbound
Nourthbound
AMB
AMB
AMB
AMB
n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Preliminary Data Sheet E1010E20 (Ver. 2.0)
5
Secondary or to
optional next FBD
Primary or Host
Direction
n/c
京公网安备 11010802033920号
EEWORLD
