• Easy memory expansion with CE1, CE2 and OE inputs
• TTL-compatible, three-state I/O
• Ideal for cache and portable computing
- 75% power reduction during CPU idle mode
• 32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
• ESD protection >2000 volts
• Latch-up current >200 mA
Logic block diagram
Vcc
GND
Input buffer
Pin arrangement
DIP, SOJ
A0
A1
A2
A3
A4
A5
A6
A7
Row decoder
256×256×8
Array
(524,288)
Sense amp
I/O0
WE
Column decoder
Control
circuit
OE
CE1
CE2
A A A A A A A A
8 9 10 11 12 13 14 15
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
L
7C3512-12
12
3
70
2.5
0.5
7C3512-15
15
4
65
2.5
0.5
7C3512-20
20
5
60
2.5
0.5
7C3512-25
25
6
55
2.5
0.5
AS7C3512
I/O7
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
7C3512-35
35
8
50
2.5
0.5
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
AS7C3512
AS7C3512L
Functional description
The AS7C3512 is a 3.3V high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized as 65,536 words × 8 bits.
It is designed for memory applications requiring fast data access at low voltage, including Pentium
™
, PowerPC
™
, and portable computing.
Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when CE1 is HIGH or CE2 is LOW. CMOS standby mode consumes
≤9.0
mW (≤1.8 mW for the L version).
Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and
stretch mode. Both versions of the AS7C3512 offer 2.0V data retention.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20/25/35 ns with output enable access times (t
OE
) of 3/4/5/6/8 ns are ideal
for high performance applications. The active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank
memory systems.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external
devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C3512 is packaged in
all high volume industry standard packages.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND
Power dissipation
Storage temperature (plastic)
Temperature under bias
DC output current
Symbol
V
CC
V
IN
P
D
T
stg
T
bias
I
out
Min
–0.5
–0.5
–
–55
–10
–
Max
+4.6
+6.0
1.0
+150
+85
20
Unit
V
V
W
o
C
o
C
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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