August 2004
rev 2.0
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clocking signal at the
output.
Integrated loop filter components.
Operates with a 3.3V ±10% supply.
Operating current less than 6mA.
Low power CMOS design.
Input frequency range: 6MHz to 12MHz.
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Frequency deviation: ±1%.
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages and 5-pin TSOT package.
ASM3P2669A
The ASM3P2669A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2669A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2669A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Product Description
The ASM3P2669A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2669A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of
all clock
dependent signals. The ASM3P2669A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
Key Specifications
Description
Supply voltages
Frequency Range
Cycle-to-Cycle Jitter
Output Duty Cycle
Output Rise and Fall Time
Modulation Rate Equation
Frequency Deviation
Specification
V
DD
= 3.3V ±10%
6MHz < CLKIN < 12MHz
300 ps (maximum)
40/60% (worst case)
1.1 ns (maximum)
F
IN
/256
±1%
VDD
Block Diagram
PD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Pin Configuration (6-pin TSOT-23)
PD
1
NC
2
CLKIN
3
6
ASM3P2669A
VSS
ModOUT
VDD
ASM3P2669A
5
4
Pin#
1
2
3
4
5
6
Pin Name
PD
NC
CLKIN
VDD
ModOUT
VSS
Type
I
-
I
P
O
P
Description
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used.
No connect.
External reference frequency input.
Power supply for the entire chip (3.3V)
Spread spectrum clock output.
Ground connection.
Pin Configuration (8-pin SOIC and TSSOP)
CLKIN
1
NC
2
8
7
VDD
NC
ModOUT
VSS
ASM3P2669A
PD
3
NC
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
CLKIN
NC
PD
NC
VSS
ModOUT
NC
VDD
Type
I
-
I
-
P
O
-
P
External reference frequency input.
No Connect.
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used.
No connect.
Ground connection.
Spread spectrum clock output.
No connect.
Power supply for the entire chip (3.3V)
Description
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
2 of 9
August 2004
rev 2.0
Modulation Profile
ASM3P2669A
Specification
Description
Frequency Range
Modulation Equation
Frequency Deviation
Specification
6MHz < CLKIN < 12MHz
F
IN
/256
±1%
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Voltage on any pin with respect to Ground
V
DD
, V
IN
0.5 to +7.0
V
Storage temperature
T
STG
-65 to +125
°C
Operating temperature
T
A
0 to 70
°C
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings
for prolonged periods of time may affect device reliability.
DC Electrical Characteristics
(Test conditions: All parameters are measured at room temperature (25°C) unless otherwise stated.)
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
PD
Input low voltage
Input high voltage
Input low current
Input high current
Parameter
Min
GND - 0.3
2.0
–
–
Typ
–
–
–
–
–
–
–
–
–
3.3
–
50
Max
0.8
V
DD
+ 0.3
-35
35
0.4
–
1.5
1.0
6
3.6
10
–
Unit
V
V
µA
µA
V
V
mA
µA
mA
V
mS
ù
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
–
Output high voltage (V
DD
= 3.3 V, I
OH
= 20 mA)
2.5
Static supply current*
–
Power-down current**
–
Dynamic supply current (3.3V, 12MHz and 15pF
I
CC
–
loading)
V
DD
Operating voltage
3.0
t
ON
PLL first locked cycle time***
–
Z
OUT
Clock output impedance
–
*XIN/CLKIN pin is pulled low
**PD pin is pulled low
***VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
3 of 9
August 2004
rev 2.0
AC Electrical Characteristics
Symbol
CLKIN
ModOUT
t
LH
*
t
HL
*
t
JC
Input frequency
Output frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Parameter
Min
6
6
0.5
0.5
-
45
ASM3P2669A
Typ
-
-
0.7
0.7
-
50
Max
12
12
1.1
1.0
360
55
Unit
MHz
MHz
ns
ns
ps
%
t
D
Output duty cycle
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
4 of 9
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