- Single-cycle deselect also available (AS7C33256PFS16A/
AS7C33256PFS18A)
• Pentium®
*
compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power in power down mode
• NTD™
*
pipeline architecture available
(AS7C33256NTD16A/AS7C33256NTD18A)
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CS
CLR
Pin arrangement
256K × 16/18
Memory
array
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Burst logic
Q
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
18
D
CS
CLK
18
16 18
Address
register
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
16/18 16/18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
Enable
Q
delay
register
CE
CLK
Output
registers
CLK
Input
registers
CLK
ZZ
Power
down
D
CLK
OE
FT
DATA [17:0]
DATA [15:0]
Selection guide
–166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
*
–150
6.7
150
3.8
450
110
30
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Note: pins 24, 74 are NC for ×16.
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
6
166
3.5
475
130
30
Pentium
®
is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are
When driven LOW count sequence follows linear convention. This signal is
,
HIGH
internally pulled HIGH.
STATIC
ASYNC
Flow-through mode.When LOW enables single register flow-through mode.
,
Connect to V
DD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if
unused.
FT
I
I
ZZ
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
°C
°C
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
3/22/01
Alliance Semiconductor
3
AS7C33256PFD16A
AS7C33256PFD18A
®
Synchronous truth table
CE0
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
WEn
1
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Cont. read
Cont. read
Suspend read
Suspend read
Cont. read
Cont. read
Suspend read
Suspend read
Begin write
Cont. write
Cont. write
Suspend write
Suspend write
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
2
Hi−Z
Hi−Z
2
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
D
3
D
D
D
D
Key: X = Don’t Care, L = Low, H = High.
1
See “Write enable truth table” on page 2 for more information.
2
Q in flow through mode
3For write operation following a READ,
OE
must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply
voltage
2.5V I/O supply
voltage
Address and
control pins
I/O pins
Ambient operating temperature
Symbol
V
DD
V
SS
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
IH
V
IL
V
IH
V
IL
T
A
Min
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.5
*
2.0
–0.5
*
0
Nominal
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
Max
3.6
0.0
3.6
0.0
2.9
0.0
V
DD
+ 0.3
0.8
V
DDQ
+ 0.3
0.8
70
Unit
V
V
V
V
V
°C
Input voltages
†
* V
IL
min = –2.0V for pulse width less than 0.2 × t
RC
.
† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
3/22/01
ALLIANCE SEMICONDUCTOR
4
®
AS7C33256PFD16A
AS7C33256PFD18A
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)
*
Thermal resistance
(junction to top of case)
*
* This parameter is sampled.
Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Symbol
θ
JA
θ
JC
Typical
40
8
Units
°C/W
°C/W
DC electrical characteristics
–166
Parameter
Input leakage
current
*
Output leakage
current
Operating power
supply current
Symbol
|I
LI
|
|I
LO
|
I
CC
I
SB
Standby power
supply current
I
SB1
I
SB2
Output voltage
V
OL
V
OH
Test conditions
V
DD
= Max, V
IN
= GND to V
DD
OE
≥
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
CE0 = V
IL
, CE1 = V
IH
, CE2 = V
IL
,
f = f
Max
, I
OUT
= 0 mA
Deselected, f = f
Max
, ZZ
≤
V
IL
Deselected, f = 0, ZZ
≤
0.2V
all V
IN
≤
0.2V or
≥
V
DD
– 0.2V
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V
All V
IN
≤
V
IL
or
≥
V
IH
I
OL
= 8 mA, V
DDQ
= 3.465V
I
OH
= –4 mA, V
DDQ
= 3.135V
–150
–133
–100
Min Max Min Max Min Max Min Max Unit
–
–
–
–
–
–
–
2.4
2
2
475
130
30
30
0.4
–
–
–
–
–
–
–
–
2.4
2
2
450
110
30
30
0.4
–
–
–
–
–
–
–
–
2.4
2
2
425
100
30
30
0.4
–
–
–
–
–
–
–
–
2.4
2
2
325
90
30
30
0.4
–
V
mA
µA
µA
mA
* LBO pin has an internal pull-up and input leakage = ±10
µa.
Note: ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
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