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AS29F010-70LC

Description
Flash, 128KX8, 70ns, PQCC32
Categorystorage    storage   
File Size155KB,12 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS29F010-70LC Overview

Flash, 128KX8, 70ns, PQCC32

AS29F010-70LC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
package instructionQCCJ, LDCC32,.5X.6
Reach Compliance Codeunknown
Maximum access time70 ns
command user interfaceYES
Data pollingYES
JESD-30 codeR-PQCC-J32
JESD-609 codee0
memory density1048576 bit
Memory IC TypeFLASH
memory width8
Number of departments/size4
Number of terminals32
word count131072 words
character code128000
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Department size32K
Maximum standby current0.001 A
Maximum slew rate0.05 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
switch bitYES
typeNOR TYPE
Base Number Matches1
High Performance
128K×8
CMOS Flash EEPROM
5V 128K×8 CMOS Flash Memory
FEATURES
• Organization:131,072 words × 8 bits
• Sector Erase architecture
– Four 32K × 8 sectors
• Single 5.0±0.5V power supply
• High speed 70/90/120/150 ns address access time
• Low power consumption:
– 30 mA maximum read current
– 50 mA maximum program current
– 1.5 mA maximum standby current
– 1 mA maximum standby current (low power)
• Deep power-down: I
CC
< 2µA (AS29F011 version)
• 10,000 write/erase cycle endurance
– Data polling
– I/O6 toggle
• Low V
CC
write lock-out below 3.2V
• JEDEC standard packages and pinouts:
– 32-pin DIP
– 32-pin PLCC
– 32-pin TSOP
• JEDEC standard write cycle commands
– protects data from accidental changes
• Program/erase cycle end signals:
AS29F010
AS29F011
LOGIC BLOCK DIAGRAM
I/O
0
~I/O
7
V
CC
GND
PIN ARRANGEMENT
Pin
Description
address inputs
data input/output
chip enable
output enable
write enable
device ground
power supply
no connect
deep power down
(AS29F011 only)
TSOP
A11
A9
A8
A13
A14
NC*
WE
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A[16:0]
I/O[7:1]
CE
OE
WE
GND
V
CC
NC
RP
Erase Voltage
Switch
State
Control
Command
Register
Program Voltage
Switch
Input/Output
Buffers
WE
AS29F010
Data
Latch
CE
OE
Chip Enable
Output Enable
Logic
PDIP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE(W)
NC*
A14
A13
A8
A9
A11
OE
A10
CE(E)
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC
A12
A15
A16
NC
V
CC
WE (W)
NC*
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
Low V
CC
Detector
A
0
~A
16
Address Latch
Program/Erase
Pulse Timer
Y-Decoder
Y-Gating
X-Decoder
1,048,576 bit
Cell Matrix
AS29F010
A14
A13
A8
A9
A11
OE (G)
A10
CE (E)
I/O7
AS29F010
AS29F010-01
*RP pin for
AS29F011
SELECTION GUIDE
29F010-70
Maximum access time
Chip enable access time
Output enable access time
t
AA
t
CE
t
OE
70
70
30
29F010-90
90
90
35
29F010-120
120
120
50
29F010-150
150
150
50
Unit
ns
ns
ns
ALLIANCE SEMICONDUCTOR
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
14
15
16
17
18
19
20
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