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ISL72991RH
Application Information
Typical User Application:
VIN
VIN
ILIM
SD
GND
VOUT
Capacitor Selection
VOUT
ISL72991RH
ADJ
An input capacitor is required if the regulator is located more
than 6 inches from power supply filter capacitors. A 10µF
solid tantalum capacitor is recommended.
An output capacitor of at least 10µF must be used to insure
stability of the regulator. Additional capacitance may be
added as required to improve the dynamic response of the
regulator. Solid tantalum and/or ceramic capacitors are
recommended.
RCL
CIN
R2
FIGURE 1. TYPICAL APPLICATION SCHEMATIC
R1
CC
COUT
Output Voltage Programming
The output voltage of the regulator can be programmed with
two external resistors and is described by the following
equation: V
OUT
= V
REF
x (1+R2/R1) - (I
ADJ
x R2).
Loop Compensation
The output capacitor and ESR comprise a zero in the loop
transfer function that must be compensated with a pole to
insure loop stability in accordance with the following
equation: C
C
x R2 = C
OUT
x ESR. The compensating
capacitor should be a low ESR ceramic type.
Output Current Limit Programming
The output current limit threshold of the regulator can be
programmed with a single external resistor connected from
I
LIM
to ground. The current flowing into the I
LIM
pin is
described by the following equation: I
LIM
= 1V/(R
CL
+ 2400).
The graph below shows the relationship between I
LIM
and
the output current limit threshold, I
OUT_LIM
.
Layout Guidelines
The stability of the regulator is sensitive to layout. It is
strongly recommended that a continuous copper ground
plane (1 ounce or greater) be used. In addition, component
lead lengths and interconnects should be minimized, but
should not exceed 1/2 inch. Finally, the return lead of the
compensation capacitor (C
C
) should be connected as close
as possible to the GND pin of the IC.
I
OUT_LIM
(A)
I
LIM
(A)
FIGURE 2. I
OUT_LIM
vs I
LIM
2
ISL72991RH
Die Characteristics
DIE DIMENSIONS:
5870µm x 5210µm (231.1mils x 205.1mils)
Thickness: 483µm
±
25.4µm (19mils
±
1mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ
±
1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ
±
2kÅ
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
Metallization Mask Layout
ISL72991RH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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