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5962G9657801QXC

Description
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20, BOTTOM BRAZED, CERAMIC, DFP-20
Categorylogic    logic   
File Size233KB,10 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962G9657801QXC Overview

D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20, BOTTOM BRAZED, CERAMIC, DFP-20

5962G9657801QXC Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionBOTTOM BRAZED, CERAMIC, DFP-20
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-CDFP-F20
JESD-609 codee4
Logic integrated circuit typeD FLIP-FLOP
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)19 ns
Certification statusQualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose500k Rad(Si) V
Trigger typePOSITIVE EDGE
width6.9215 mm
Base Number Matches1
Standard Products
UT54ACS273/UT54ACTS273
Octal D-Flip-Flops with Clear
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Contains eight flip-flops with single-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
- Buffer/storage registers, shift registers, and pattern
generators
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS273 - SMD 5962-96578
UT54ACTS273 - SMD 5962-96579
DESCRIPTION
The UT54ACS273 and the UT54ACTS273 are positive-edge-
triggered D-type flip-flops with a direct clear input.
Information at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse. When the clock input is at either the high or low
level, the D input signal has no effect at the output.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
CLK
X
L
D
x
X
H
L
X
OUTPUTS
PINOUTS
20-Pin DIP
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
20-Lead Flatpack
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
LOGIC SYMBOL
Q
x
L
H
L
No change
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
(1)
(11)
(3)
(4)
(7)
(8)
(13)
(14)
(17)
(18)
1D
R
C1
(2)
(5)
(6)
1Q
2Q
3Q
(9)
4Q
(12)
5Q
(15)
6Q
(16)
7Q
(19)
8Q
1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
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