ACS245MS
January 1996
Radiation Hardened Octal
Non-Inverting Bidirectional Bus Transceiver
Pinouts
20 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835
DESIGNATOR CDIP2-T20, LEAD FINISH C
TOP VIEW
DIR
A0
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
9
20 VCC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96707 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
-10
Errors/Bit/Day
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
≤
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)
12
RAD (Si)/s, 20ns Pulse
A7
GND 10
20 PIN CERAMIC FLATPACK, MIL-STD-1835
DESIGNATOR CDFP4-F20, LEAD FINISH C
TOP VIEW
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OE
B0
B1
B2
B3
B4
B5
B6
B7
Description
The Intersil ACS245MS is a Radiation Hardened octal non-inverting
bidirectional bus transceiver intended for two-way asynchronous
communication between data busses.
The ACS245MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS245MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
Dual-In-Line Ceramic Package (D suffix).
Ordering Information
PART NUMBER
5962F9670701VRC
5962F9670701VXC
ACS245D/Sample
ACS245K/Sample
ACS245HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518780
3198.1
ACS245MS
Functional Diagram
NOTE: (1 of 8)
P
N
A
B
P
N
OE
DIR
TRUTH TABLE
INPUTS
OE
L
L
H
NOTE:
H = High Voltage Level, L = Low Voltage Level, X = Immaterial
DIR
L
H
X
OPERATION
B Data to A Bus
A Data to B Bus
Isolation
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Spec Number
2
518780
FPGA/CPLD
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