ACS280MS
January 1996
Radiation Hardened 9-Bit Odd/
Even Parity Generator Checker
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
I6 1
I7 2
NC 3
I8 4
EVEN 5
ODD 6
GND 7
14 VCC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96708 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
≤
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 23ns (Max), 15ns (Typ)
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
I6
I7
NC
I8
EVEN
ODD
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
I5
I4
I3
I2
I1
I0
Description
The Intersil ACS280MS is a Radiation Hardened 9-bit odd/even parity
generator checker device. Both odd and even parity outputs are available
for generating or checking parity for words up to 9 bits long. Even parity
is indicated (EVEN output high) when an even number of data inputs are
high. Odd parity is indicated (ODD output high) when an odd number of
data inputs are high. Parity checking for larger words can be accom-
plished by tying EVEN output to any input of an additional ACS280MS.
The ACS280MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9670801VCC
5962F9670801VXC
ACS280D/Sample
ACS280K/Sample
ACS280HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518819
3568.1
ACS280MS
Functional Diagram
I8 (4)
I7 (2)
I6 (1)
ÂE (5)
I5 (13)
I4 (12)
I3 (11)
ÂO (6)
I2 (10)
I1 (9)
I0 (8)
NC = 3
VDD = 14
GND = 7
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Spec Number
2
518819
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