ACTS112MS
January 1996
Radiation Hardened
Dual J-K Flip-Flop
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
CP1 1
K1 2
J1 3
S1 4
Q1 5
Q1 6
Q2 7
GND 8
16 VCC
15 R1
14 R2
13 CP2
12 K2
11 J2
10 S2
9 Q2
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96714 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
≤
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 26ns (Max), 16ns (Typ)
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
CP1
K1
J1
S1
Q1
Q1
Q2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
Description
The Intersil ACTS112MS is a Radiation Hardened Dual J-K Flip-Flop
with Set and Reset. The output change states on the negative transition
of the clock (CP1N or CP2N).
The ACTS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9671401VEC
5962F9671401VXC
ACTS112D/Sample
ACTS112K/Sample
ACTS112HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518825
3570.1
ACTS112MS
Functional Diagram
5 (9)
CL
Q
P
3(11)
J
CL
P
N
2(12)
K
4(10)
S
15(14)
R
1(13)
CL
CP
CL
CL
N
CL
CL
P
N
CL
CL
P
N
6 (7)
CL
Q
TRUTH TABLE
INPUTS
S
L
H
L
H
H
H
H
H
NOTE:
1. H = High Steady State, L = Low Steady State, X = Immaterial,
= High-to-Low Transition
R
H
L
L
H
H
H
H
H
H
CP
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
H
L
Toggle
No Change
Q
H
L
H (Note 2)
OUTPUTS
Q
L
H
H (Note 2)
No Change
L
H
2. Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the
Same Time
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Spec Number
2
518825
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