B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-strap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 50µA out of this pin to maintain
bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 15V.
High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 18V (no greater than V
DD
). An internal 100µA pull-up to V
DD
will hold HEN high, so
no connection is required if high-side and low-side outputs are to be controlled by IN+/IN -inputs.
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When
DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 18V (no
greater than V
DD
). An internal 100µA pull-up to V
DD
will hold DIS high if this pin is not driven.
Chip negative supply, generally will be ground.
OUTput of the input control comparator. This rail to rail output signal can be used for feedback and hysteresis.
Noninverting input of control comparator. This pin can only be driven by signal levels of 0V to 5.5V. If IN+ is greater
than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than
IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will
override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When
switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).
Inverting input of control comparator. This pin can only be driven by signal levels of 0V to 5.5V. See IN+ (Pin 6)
description.
High-side turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
Low-side turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the turn-on delay of
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-
through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-strap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain
bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 15V.
A High-side Output. Connect to gate of A High-side power MOSFET.
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap
capacitor to this pin.
A Low-side Output. Connect to gate of A Low-side power MOSFET.
A Low-side Source connection. Connect to source of A Low-side power MOSFET.
Positive supply to gate drivers. Must be same potential as V
DD
(Pin 16). Connect to anodes of two bootstrap diodes.
Positive supply to lower gate drivers. Must be same potential as V
CC
(Pin 15). De-couple this pin to V
SS
(Pin 4).
B Low-side Source connection. Connect to source of B Low-side power MOSFET.
B Low-side Output. Connect to gate of B Low-side power MOSFET.
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap
capacitor to this pin.
B High-side Output. Connect to gate of B High-side power MOSFET.
2
HEN
3
DIS
4
5
6
V
SS
OUT
IN+
7
IN-
8
HDEL
9
LDEL
10
AHB
11
12
AHO
AHS
13
14
15
16
17
18
19
ALO
ALS
V
CC
V
DD
BLS
BLO
BHS
20
BHO
2
HS-4080ARH
Application Block Diagram
80V
12V
BHO
BHS
HEN
DIS
HS-4080ARH
IN+
IN-
ALO
AHS
AHO
BLO
LOAD
GND
GND
Typical Application (Hysteresis Mode Switching)
80V
1 BHB
12V
DIS
2 HEN
3 DIS
HS-4080ARH
4 V
SS
5 OUT
6V
IN
6 IN+
7 IN-
8 HDEL
9 LDEL
10 AHB
BHO 20
BHS 19
BLO 18
BLS 17
V
DD
16
V
CC
15
ALS 14
ALO 13
AHS 12
AHO 11
12V
LOAD
GND
-
+
6V
GND
3
HS-4080ARH
Die Characteristics
DIE DIMENSIONS:
4760µm x 5660µm (188 mils x 223 mils)
Thickness: 483µm
±25.4µm
(19 mils
±1
mil)
INTERFACE MATERIALS:
Glassivation:
Type: Phosphorus Silicon Glass
Thickness: 8.0k
Å
±1.0k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
±2k
Å
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
432
Metallization Mask Layout
HS-4080ARH
16
17
18
15
14
13
19
20
1
12
11
10
9
2
8
3
7
4
5
6
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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