Operational environment: total dose irradiation testing to MIL-
STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 16-lead flatpack (0.7 grams)
Standard Microcircuit Drawing 5962-95834
- QML Q and V compliant part
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
INTRODUCTION
The UT54LVDS032 Quad Receiver is a quad CMOS differential
line receiver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The UT54LVDS032 accepts low voltage (340mV) differential
input signals and translates them to 5V TTL output levels. The
receiver supports a three-state function that may be used to
multiplex outputs. The receiver also supports OPEN, shorted and
terminated (100) input fail-safe. Receiver output will be HIGH
for all fail-safe conditions.
The UT54LVDS032 and companion quad line driver
UT54LVDS031 provide new alternatives to high power pseudo-
ECL devices for high speed point-to-point interface applications.
R
IN1+
R
IN1-
+
R1
-
R
OUT1
R
IN2+
R
IN2-
+
R2
-
R
OUT2
R
IN3+
R
IN3-
+
R3
-
R
OUT3
R
IN4+
R
IN4-
EN
EN
+
R4
-
R
OUT4
Figure 1. UT54LVDS032 Quad Receiver Block Diagram
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Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
APPLICATIONS INFORMATION
The UT54LVDS032 receiver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in Figure
3. This configuration provides a clean signaling environment for
quick edge rates of the drivers. The receiver is connected to the
driver through a balanced media which may be a standard twisted
pair cable, a parallel pair cable, or simply PCB traces. Typically,
the characteristic impedance of the media is in the range of 100.
A termination resistor of 100should be selected to match the
media and is located as close to the receiver input pins as possible.
The termination resistor converts the current sourced by the driver
into voltages that are detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the effects
of a mid-stream connector(s), cable stub(s), and other impedance
discontinuities, as well as ground shifting, noise margin limits, and
total termination loading must be taken into account.
R
IN1-
R
IN1+
R
OUT1
EN
R
OUT2
R
IN2+
R
IN2-
V
SS
1
2
3
4
5
6
7
8
UT54LVDS032
Receiver
16
15
14
13
12
11
10
9
V
DD
R
IN4-
R
IN4+
R
OUT4
EN
R
OUT3
R
IN3+
R
IN3-
Figure 2. UT54LVDS032 Pinout
ENABLE
TRUTH TABLE
Enables
EN
L
EN
H
Input
R
IN+
- R
IN
-
X
V
ID
> 0.1V
V
ID
< -0.1V
Full Fail-safe
OPEN/SHORT or
Terminated
PIN DESCRIPTION
Pin No.
2, 6, 10, 14
1, 7, 9, 15
3, 5, 11, 13
4
12
16
8
Name
R
IN+
R
IN-
R
OUT
EN
EN
V
DD
V
SS
Description
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
Active high enable pin, OR-ed
with EN
Active low enable pin, OR-ed
with EN
Power supply pin, +5V + 10%
Ground pin
Output
R
OUT
Z
H
L
H
DATA
INPUT
1/4 UT54LVDS031
RT 100
1/4 UT54LVDS032
+
-
DATA
OUTPUT
Figure 3. Point-to-Point Application
All other combinations
of ENABLE inputs
The UT54LVDS032 differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the result of a ground potential difference
between the driver’s ground reference and the receiver’s ground
reference, the common-mode effects of coupled noise or a
combination of the two. Both receiver input pins should honor their
specified operating input voltage range of 0V to +2.4V (measured
from each pin to ground).
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Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
Receiver Fail-Safe
The UT54LVDS032 receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to TTL logic levels.
Due to the high gain and tight threshold of the receiver, care should
be taken to prevent noise from appearing as a valid signal.
The receiver’s internal fail-safe circuitry is designed to source/sink
a small amount of current, providing fail-safe protection (a stable
known state of HIGH output voltage) for floating, terminated or
shorted receiver inputs.
1.
Open Input Pins.
The UT54LVDS032 is a quad receiver
device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or any
other voltages. The input is biased by internal high value
pull up and pull down resistors to set the output to a HIGH
state. This internal circuitry will guarantee a HIGH, stable
output state for open inputs.
2.
Terminated Input.
If the driver is disconnected (cable
unplugged), or if the driver is in a three-state condition, the
receiver output will again be in a HIGH state, even with the
end of cable 100 termination resistor across the input pins.
The unplugged cable can become a floating antenna which
can pick up noise. If the cable picks up more than 10mV of
differential noise, the receiver may see the noise as a valid
signal and switch. To insure that any noise is seen as
common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable offers better
balance than flat ribbon cable.
3.
Shorted Inputs.
If a fault condition occurs that shorts the
receiver inputs together, thus resulting in a 0V differential
input voltage, the receiver output remains in a HIGH state.
Shorted input fail-safe is not supported across the common-
mode range of the device (V
SS
to 2.4V). It is only supported
with inputs shorted and no external common-mode voltage
applied.
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Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
Neutron Fluence
1
Notes:
1. Guarnteed but not tested.
LIMIT
1.0E6
>100
1.0E13
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 6.0V
-0.3 to (V
DD
+ 0.3V)
-65 to +150C
1.25 W
+150C
10C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage, receiver inputs
DC input voltage, logic inputs
LIMITS
4.5 to 5.5V
-55 to +125C
2.4V
0 to V
DD
for EN, EN
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Cobham Semiconductor Solutions
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DC ELECTRICAL CHARACTERISTICS *
1
SYMBOL
V
IH
V
IL
V
OL
V
OH
I
IN
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Logic input leakage current
(TTL)
(TTL)
(V
DD
= 5.0V +10%; -55C < T
C
< +125C); Unless otherwise
CONDITION
MIN
2.0
0.8
0.3
4.0
-10
-10
+10
+10
MAX
UNIT
V
V
V
V
A
I
OL
= 2mA, V
DD
= 4.5V
I
OH
= -0.4mA, V
DD
= 4.5V
Inputs, V
IN
= 0 and 2.4V, V
CC
= 5.5
Enables = EN/EN= 0 and 5.5V,
V
CC
= 5.5
V
CM
= +1.2V
V
CM
= +1.2V
V
IN
= 2.4V
Disabled, V
OUT
= 0 V or V
DD
I
CL
= +/-18mA
Enabled, V
OUT
= 0 V
2
EN, EN = V
DD
or V
SS
Inputs Open
EN = V
SS
, EN = V
DD
Inputs Open
-100
-10
-10
-1.5
-15
V
TH3
V
TL3
I
I
I
OZ4
V
CL
I
OS3
I
CC4
I
CCZ4
Differential Input High Threshold
Differential Input Low Threshold
Receiver input Current
Output Three-State Current
Input clamp voltage
Output Short Circuit Current
Loaded supply current receivers
enabled
Loaded supply current receivers
disabled
+100
mV
mV
+10
+10
1.5
-130
11
V
mA
mA
mA
11
noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum
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FPGA/CPLD
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