STK14C88
32Kx8 AutoStore nvSRAM
Features
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Description
The Cypress STK14C88 is a 256 Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
The SRAM provides the fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
Data automatically transfers to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
25, 35, 45 ns Read Access and R/W Cycle Time
Unlimited Read/Write Endurance
Automatic Nonvolatile STORE on Power Loss
Nonvolatile STORE Under Hardware or Software Control
Automatic RECALL to SRAM on Power Up
Unlimited RECALL Cycles
1 Million STORE Cycles
100-Year Nonvolatile Data Retention
Single 5V+10% Power Supply
Commercial, Industrial, Military Temperatures
32-Pin 300 mil SOIC (RoHS-Compliant)
32-Pin CDIP and LCC Packages
Logic Block Diagram
fo
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d
V
CCX
V
CAP
Quantum Trap
512 x 512
STORE
STORE/
RECALL
CONTROL
HSB
POWER
CONTROL
ROW DECODER
ec
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
m
om
STATIC RAM
ARRAY
512 x 512
RECALL
ew
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
13
A
0
A
1
A
2
A
3
A
4
A
10
G
E
W
R
INPUT BUFFERS
N
ot
Cypress Semiconductor Corporation
Document Number: 001-52038 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 01, 2009
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STK14C88
Contents
Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
DC Characteristics .............................................................. 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
SRAM Read Cycles #1 and #2 ............................................ 6
SRAM Write Cycle #1 and #2 .............................................. 7
Hardware Mode Selection................................................... 8
Hardware STORE Cycle ...................................................... 8
AutoStore/Power up RECALL ............................................ 9
nvSRAM Operation............................................................ 10
Noise Considerations........................................................ 10
SRAM Read ........................................................................ 10
SRAM Write ........................................................................
Power Up RECALL ............................................................
Software Nonvolatile STORE............................................
Software Nonvolatile RECALL .........................................
AutoStore Mode.................................................................
AutoStore INHIBIT Mode...................................................
HSB Operation ...................................................................
Best Practices....................................................................
Preventing STORES ..........................................................
Hardware Protect...............................................................
Low Average Active Power...............................................
Software STORE/RECALL Mode Selection .....................
Software-Controlled STORE/RECALL Cycle...................
Ordering Information.........................................................
Document History Page ....................................................
Sales, Solutions, and Legal Information .........................
Worldwide Sales and Design Support..........................
Products .......................................................................
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Document Number: 001-52038 Rev. *B
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STK14C88
Pin Configurations
Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP
Figure 2. Pin Diagram - 32-Pin 450 Mil LCC
A
12
A
14
A
7
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
HSB
W
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
W
1
32
V
CC
HSB
V
CCx
V
Cap
V
CAP
A
13
A
8
A
9
G
(TOP)
es
i
D
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
V
SS
(TOP)
Pin Descriptions
Pin Name
A
14
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
I/O
Input
I/O
Input
Input
Input
Address:
The 15 address inputs select one of 32,768 bytes in the nvSRAM array.
Chip Enable:
The active low E input selects the device.
Power Supply
Power:
5.0V, +10%.
N
V
CAP
V
SS
NC
Power Supply
AutoStore Capacitor:
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile storage elements.
Power Supply
Ground.
No Connect
Unlabeled pins have no internal connections.
Document Number: 001-52038 Rev. *B
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I/O
R
ec
Write Enable:
The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E.
Output Enable:
The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tristate.
Hardware Store Busy:
When low this output indicates a Store is in progress. When pulled
low external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (optional connection).
om
Data:
Bi-directional 8-bit data bus for accessing the nvSRAM.
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A
11
NC
A
10
E
DQ
7
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STK14C88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 7.0V
Voltage on Input Relative to V
SS
...........–0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
or HSB ......................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Storage Temperature .................................... –65°C to 150°C
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
Note
Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Over the operating range (V
CC
= 5.0V ± 10%)
[4]
Symbol
I
CC1[1]
Parameter
Average V
CC
Current
Commercial
Min
Max
97
80
70
3
10
Industrial/
Military
Min
Max
100
85
70
3
10
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Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
V
V
V
All Inputs
All Inputs
V
V
°C
gn
Notes
DC Characteristics
D
t
AVAV
= 25 ns
t
AVAV
= 35 ns
t
AVAV
= 45 ns
All Inputs Don’t Care, V
CC
=
max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS
Levels
All Inputs Don’t Care
t
AVAV
= 25 ns, E
≥
V
IH
t
AVAV
= 35 ns, E
≥
V
IH
t
AVAV
= 45 ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
2
31
26
23
1.5
±1
±5
0.8
I
OUT
= – 4 mA except HSB
I
OUT
= 8 mA except HSB
I
OUT
= 3 mA
0.4
0.4
I
CC2[2]
I
CC3[1]
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
=
200 ns
5V, 25°C, Typical
Average V
CAP
Current during
AutoStore Cycle
Average V
CC
Current
(Standby, Cycling TTL Input
Levels)
I
CC4[2]
I
SB1[3]
om
I
SB2[3]
V
CC
Standby Current
(Standby, Stable CMOS Input
Levels)
m
ec
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
V
BL
T
A
Input Leakage Current
N
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
ot
Input Logic “1” Voltage
R
Off-State Output Leakage Current
2.2
V
SS
– .5
2.4
en
de
d
V
CC
+ 0.5
0.8
fo
2
30
25
22
1.5
±1
±5
2.2
V
SS
– .5
2.4
0.4
0.4
0
70
-40/-55
rN
Notes
1. I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
2. I
CC2
and I
CC4
are the average currents required for the duration of the respective STORE cycles (t
STORE
).
3. E
≥
V
IH
does not produce standby current levels until any nonvolatile cycle in progress has timed out.
4. V
CC
reference levels throughout this data sheet refer to V
CC
if that is where the power supply connection is made, or V
CAP
if V
CC
is connected to ground.
Document Number: 001-52038 Rev. *B
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V
CC
+0.5
85/125
s
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STK14C88
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load....................................................... See
Figure 3
Figure 3. AC Output Loading
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Capacitance
Parameter
[5]
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
T
A
= 25°C, f = 1 MHz,
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Test Conditions
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Max
5
7
Unit
pF
pF
D
Conditions
ΔV
= 0 to 3V
ΔV
= 0 to 3V
Note
5. These parameters are guaranteed but not tested.
Document Number: 001-52038 Rev. *B
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480 Ohms
gn
5.0V
s
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