Cache SRAM, 512KX8, 25ns, CMOS, CDIP32, 1.600 X 0.600 INCH, 0.200 INCH HEIGHT, HERMETIC SEALED, CERAMIC, DIP-32
| Parameter Name | Attribute value |
| Maker | Cobham Semiconductor Solutions |
| Parts packaging code | DIP |
| package instruction | DIP, |
| Contacts | 32 |
| Reach Compliance Code | unknown |
| ECCN code | 3A001.A.2.C |
| Maximum access time | 25 ns |
| Other features | TTL COMPATIBLE INPUTS/OUTPUTS |
| JESD-30 code | R-CDIP-T32 |
| JESD-609 code | e4 |
| memory density | 4194304 bit |
| Memory IC Type | CACHE SRAM |
| memory width | 8 |
| Number of functions | 1 |
| Number of terminals | 32 |
| word count | 524288 words |
| character code | 512000 |
| Operating mode | ASYNCHRONOUS |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 512KX8 |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | DIP |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Parallel/Serial | PARALLEL |
| Certification status | Not Qualified |
| Filter level | MIL-STD-883 |
| Maximum seat height | 5.715 mm |
| Maximum supply voltage (Vsup) | 5.5 V |
| Minimum supply voltage (Vsup) | 4.5 V |
| Nominal supply voltage (Vsup) | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | GOLD |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| width | 15.24 mm |
| Base Number Matches | 1 |
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