5962H8957701VXA datasheet, PDF

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5962H8957701VXA: DescriptionBCRTM; File Size1MB，61 Pages; ManufacturerETC

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5962H8957701VXA Overview

BCRTM

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UT1553 BCRTM

EATURES

Comprehensive MIL-STD-1553 dual-redundant Bus

Controller (BC) and Remote Terminal (RT) and

Monitor (M) functions

MIL-STD-1773 compatible

Multiple message processing capability in BC

Time tagging and message logging in RT and M modes

Automatic polling and intermessage delay in

BC mode

Programmable interrupt scheme and internally

generated interrupt history list

programmability

DMA memory interface with 64K addressability

Internal self-test

Radiation-hardened option available for 84-lead

flatpack package only

Remote terminal operations in ASD/ENASD-certified

(SEAFAC)

Available in 84-pin pingrid array, 84-lead flatpack, 84-

lead leadless chip-carrier

Standard Microcircuit Drawing 5962-89577 available

- QML Q and V compliant

REGISTERS

CONTROL

HIGH-PRIORITY

STD PRIORITY LEVEL

STD PRIORITY PULSE

STATUS

CURRENT BC (or M) BLOCK/

RT DESCRIPTOR SPACE

POLLING COMPARE

CLOCK &

RESET

LOGIC

INTERRUPT

HANDLER

BC PROTOCOL

MESSAGE

HANDLER

BUILT-IN-TEST WORD

CURRENT COMMAND

INTERRUPT LOG

LIST POINTER

HIGH-PRIORITY

INTERRUPT ENABLE

HIGH-PRIORITY

INTERRUPT STATUS

STANDARD INTERRUPT

ENABLE

RT/MONITOR

PROTOCOL &

MESSAGE

HANDLER

BUILT-

IN-

TEST

RT ADDRESS

BUILT-IN-TEST

START COMMAND

RESET COMMAND

RT TIMER

RESET COMMAND

MONITOR ADDRESS

CONTROL

MONITOR ADDRESS

SELECT (0-15)

ADDRESS

MONITOR ADDRESS

SELECT (16-31)

DATA

12MHz

MASTER

RESET

1553

DATA

CHANNEL

1553

DATA

CHANNEL

DUAL

CHANNEL

ENCODER/

DECODER

MODULE

PARALLEL-

TO-SERIAL

CONVER-

SION

BUS

TRANSFER

LOGIC

SERIAL-TO-

PARALLEL

CONVER-

SION

TIMERON

TIMEOUT

ADDRESS

GENERATOR

DMA/CPU

CONTROL

DMA ARBITRATION

DUAL-PORT MEMORY CONTROL

Figure 1. BCRTM Block Diagram

BCRTM-1

Table of Contents

1.0

INTRODUCTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1

1.2

1.3

2.0

3.0

4.0

5.0

Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

PIN IDENTIFICATION AND DESCRIPTION

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

INTERNAL REGISTERS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SYSTEM OVERVIEW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SYSTEM INTERFACE.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

5.2

5.3

5.4

5.6

6.0

DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

REMOTE TERMINAL ARCHITECTURE.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

6.2

6.3

7.0

BUS CONTROLLER ARCHITECTURE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1

7.2

7.3

7.4

7.5

8.0

MONITOR ARCHITECTURE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1

8.2

8.3

9.0

10.0

11.0

12.0

13.0

EXCEPTION HANDLING AND INTERRUPT LOGGING

. . . . . . . . . . . . . . . . . . . . . . . . 36

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS

. . . . . . . . . . . . . . . . 40

DC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AC ELECTRICAL CHARACTERISTICS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PACKAGE OUTLINE DRAWINGS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

BCRTM-2

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