HS-3374RH
March 1996
Radiation Hardened
8-Bit Bidirectional CMOS/TTL Level Converter
Pinout
HS-3374RH
MIL-STD-1835, CDIP2-T22
(SBDIP)
TOP VIEW
VDD
A0
A1
A2
CMOS
INPUT/OUTPUT
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
22 VCC
21 B0
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 DISABLE
12 NC
TTL
INPUT/OUTPUT
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-9XXXX and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Total Dose 1 x 10
5
RAD(Si)
- Latch-Up Immune > 1 x 10
12
RAD (Si)/s (Note 1)
• Low Propagation Delay Time
- Typical CMOS to TTL Pre-RAD 40ns
- Typical CMOS to TTL Post 100K RAD 40ns
- Typical TTL to CMOS Pre-RAD 50ns
- Typical TTL to CMOS Post 100K RAD 50ns
• Low Standby Power
• +10V CMOS and +5V TTL Power Supply Inputs
• Eight Non-inverting Three-State Input/Output Channels
• No External TTL Input Pull-Up Resistors Required
• High TTL Sink Current
• Equivalent to Sandia SA2996
• Military Temperature Range -55
o
C to +125
o
C
ENABLE 10
GND 11
Description
The Intersil HS-3374RH is a radiation hardened 8-bit
bidirectional level converter designed to interface CMOS logic
levels with TTL logic levels in radiation hardened bus oriented
systems. The HS-3374RH is fabricated using a radiation
hardened EPI-CMOS process and features eight parallel
bidirectional buffer/level converters.
Two control inputs, ENABLE and DISABLE, are used to deter-
mine the direction of data flow, and to set both the in puts and
outputs in the high impedance state. The control inputs may be
driven by either TTL or CMOS logic drivers capable of sinking
one standard TTL load.
The HS-3374RH is a non-inverting version of the industry
standard CD40116. The non-inverting outputs of the
HS-3374RH reduce PC board chip count by eliminating the
need to restore data back to a non-inverted format.
NOTE:
1. For operation at 10V and transient levels above 1 x 10
10
RAD (Si)/s,
please refer to Application Note 401.
Functional Diagram
DISABLE
13
VDD = 1
VCC = 22
GND = 11
CMOS
IN/OUT
8
2-9
LEVEL
SHIFTER
8
TTL
OUT (IN)
14-21
ENABLE
10
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
HS1-3374 (SAMPLE)
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
PACKAGE
22 Lead SBDIP
22 Lead SBDIP
22 Lead SBDIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Spec Number
File Number
1
518052
3038.1
Specifications HS-3374RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11.0V
I/O Voltage Applied. . . . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
74.8
12.3
Maximum Package Power Dissipation at +125
o
C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.67W
If Device Power Exceeds Package Dissipation Capability, Provide
Heat Sinking or Derate Linearly at the Following Rate:
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4mW/
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
VDD . . . . . . . . . . . . . +9.5V to +10.5V
VCC . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Voltage Range
Data Inputs (CMOS) . . . . . . . . . . . . . . . . . . .GND-0.3 to VDD+0.3
Data Inputs (TTL) . . . . . . . . . . . . . . . . . . . . .GND-0.3 to VCC+0.3
Enable, Disable Inputs . . . . . . . . . . . . . . . . .GND-0.3 to VDD+0.3
Operating Voltage Range
Input Low Voltage (CMOS) . . . . . . . . . . . . . . . . . . . . . . . GND to 1V
Input High Voltage (CMOS). . . . . . . . . . . . . . . . . . VDD-1.0V to VDD
Input Low Voltage (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V
Input High Voltage (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
ENABLE AND DISABLE IINPUTS
Input Leakage Current
IIH CMOS
VDD = 10.5V, VCC = 5.25V,
VIN = 10.5V, Floating Outputs
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-
1
µA
TTL INPUT TO CMOS OUTPUTS
Input Leakage Current
IIL IIH
VDD = 10.5V, VCC = 5.25V,
VIN = 0.8V, Other Inputs at 2.8V
VDD = 10.5V, VCC = 5.25V,
VIN = 2.8V, other Inputs = 0.8V
High Level Output
Voltage
VOH
VDD = 9.5V, VCC = 4.75V,
VIH = 2.8V, VIL = 0.8V,
IOH = -2.0mA
VDD = 10.5V, VCC = 5.25V,
VIH = 2.8V, VIL 0.8V,
IOL = 2.0mA
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-1
-
µA
µA
1, 2, 3
-
1
1, 2, 3
9
-
V
Low level output
Voltage
VOL
1, 2, 3
-
0.5
V
CMOS to TTL OUTPUTS
High Level Output
Voltage
VOH
VDD = 9.5, VCC = 4.75V,
VIH = 8.5V, VIL = 1.0V,
IOH = -2.0mA
VDD = 10.5V, VCC = 5.25V,
VIH = 9.5V, VIL = 1.0V,
IOL = 11mA
VDD = 10.5V, VCC = 5.25V,
VIN = 0V, All other pins high
VDD = 10.5V, VCC = 5.25V,
VIN = 2.8V, All other pins at
GND
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
3
-
V
Low Level Output
Voltage
VOL
1, 2, 3
-
0.4
V
Output Leakage
Current
IOZL
1, 2, 3
-10
-
µA
µA
IOZH
1, 2, 3
-
10
Spec Number
2
518052
Specifications HS-3374RH
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Functional Tests
SYMBOL
FT
CONDITIONS
CMOS:
1.) VDD = 10.5V, VCC = 5.25V
2.) VDD = 9.5V, VCC = 4.75V,
VIH = VDD-1V, VIL = 1V
TTL:
1.) VDD = 10.5V, VCC = 5.25V
2.) VDD = 9.5V, VCC = 4.75V,
VIH = 2.8V, VIL = 0.8V
VDD = 10.5V, VCC = 5.25V,
EN = 2.8V, DISABLE = 2.8V,
Floating Outputs
VDD = 10.5V, VCC = 5.25V, EN
= 0V, DISABLE = 2.8V, Floating
Outputs
VDD = 10.5, VCC = 5.25V,
EN = 0V, DISABLE = 2.8V,
Floating Output, Measure VCC
pin
GROUP A
SUBGROUPS
7, 8A, 8B
TEMPERATURE
-55
o
C, +25
o
C,
+125
o
C
MIN
-
MAX
-
UNITS
-
Static Current 1
SIDD1
1, 2, 3
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-55
o
C, +25
o
C,
+125
o
C
-
300
µA
Static Current 2
SIDD2
1, 2, 3
-
100
µA
Static Current
SICC
1, 2, 3
-
5
µA
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Propagation Delay Times CMOS/TTL
Data In to Data Out
Propagation Delay Times CMOS Data
In to Data Out
Propagation Delay Times CMOS/TTL
Data In to Data Out
Propagation Delay Time TTL/CMOS
Data In to Data Out
Transition Time CMOS/TTL
Input/Output
Transition Time CMOS/TTL
Input/Output
Transition Time CMOS/TTL
Input/Output
Transition Time CMOS/TTL
Input/Output
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
SYMBOL
TPHLCT
GROUP A SUB-
GROUPS
9, 10, 11
TEMPERATURE
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
MIN
-
MAX
40
UNITS
ns
TPLHCT
9, 10, 11
-
50
ns
TPHLTC
9, 10, 11
-
85
ns
TPLHTC
9, 10, 11
-
70
ns
TTHLCT
9, 10, 11
-
20
ns
TTLHCT
9, 10, 11
-
70
ns
TTHLTC
9, 10, 11
-
50
ns
TTLHTC
9, 10, 11
-
50
ns
TPHZTC
9, 10, 11
-
90
ns
TPZHTC
9, 10, 11
-
90
ns
TPLZTC
9, 10, 11
-
85
ns
Spec Number
3
518052
Specifications HS-3374RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Propagation Delay Time TTL/CMOS
Enable to CMOS Out
Propagation Delay Time CMOS/TTL
Disable to TTL Out
Propagation Delay Time CMOS/TTL
Disable to TTL Out
Propagation Delay Time CMOS/TTL
Disable to TTL Out
Propagation Delay Time CMOS/TTL
Disable to TTL Out
SYMBOL
TPZLTC
GROUP A SUB-
GROUPS
9, 10, 11
TEMPERATURE
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
MIN
-
MAX
90
UNITS
ns
TPHZCT
9, 10, 11
-
70
ns
TPZHCT
9, 10, 11
-
130
ns
TPLZCT
9, 10, 11
-
120
ns
TPZLCT
9, 10, 11
-
125
ns
NOTE: Timings are measured with the following conditions: CL = 100pF, VDD = 9.5V, VCC = 4.75V, VIH = 8.5V (2.8V), VIL = 1.0V (0.8V).
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input, Output Capacitance
SYMBOL
CMOS
CI/O
CIN
CONDITIONS
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
VDD = Open, f = 1MHz, All Measure-
ments Referenced to Device Ground
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
MIN
-
MAX
13
UNITS
pF
Input Capacitance
-
15
pF
Input, Output Capcitance
TTL
CI/O
-
17
pF
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters
are characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number
4
518052
HS-3374RH
Functional Block Diagram
1 OF 8 IDENTICAL CIRCUITS
VDD
VCC
2 (3, 4, 5, 6, 7, 8, 9)
A1 CMOS
INPUT (OUTPUT)
D
LEVEL
SHIFTER
21 (20, 19,
18, 17, 16,
15, 14)
B1 TTL
OUTPUT
(INPUT)
ENABLE
10
VCC
DISABLE
13
LEVEL
SHIFTER
D
VDD
VDD
GND
LEVEL
SHIFTER
E
VDD
E
GND
GND
GND
NOTES:
1. Enable and disable are TTL type inputs
2. D and E outputs are common to all 8 channels
INPUT (OUTPUT)
DATA
A0
A1
A2
A3
A4
A5
A6
A7
TERMINAL
NUMBER
2
3
4
5
6
7
8
9
OUTPUT (INPUT)
DATA
B0
B1
B2
B3
B4
B5
B6
B7
TERMINAL
NUMBER
21
20
19
18
17
16
15
14
ENABLE
X
1
0
DISABLE
0
1
1
TRUTH TABLE
FUNCTION
Convert CMOS Level to TTL Level
Convert TTL Level to CMOS Level
High Impedance (Z)
0 = Low Level 1 = High Level X = Don’t Care
Z = High Impedance on Both CMOS and TTL sides.
NOTE: An important caveat that is applicable to CMOS devices in
general is that unused inputs should never be left floating. This rule
applies to inputs connected to a three-state bus. The need for
external pull-up resistors during three-state bus conditions is
eliminated by the presence of regenerative latches on the following
HS-3374RH pins: A0 - 7.
The functional block diagram depicts one of these pins with the
regenerative latch. When the CMOS driver assumes the high
impedance state, the latch holds the bus in whatever logic state
(high or low) it was before the three-state condition. A transient
drive current of
±1.5mA
at VDD/2
±0.5V
for 10ns is required to
switch the latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
* WARNING: Do not activate the Disable input by hardwiring to any
TTL input pins. This is an incorrect mode of operation.
Spec Number
5
518052
FPGA/CPLD
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