ZVNL120A datasheet, PDF - EEWORLD Datasheet

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ZVNL120A: DescriptionSmall Signal Field-Effect Transistor, 0.18A I(D), 200V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-92, TO-92 COMPATIBLE, E-LINE PACKAGE-3; CategoryDiscrete semiconductor The transistor; File Size248KB，3 Pages; ManufacturerZetex Semiconductors; Websitehttp://www.zetex.com/; Environmental Compliance

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ZVNL120A Overview

Small Signal Field-Effect Transistor, 0.18A I(D), 200V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-92, TO-92 COMPATIBLE, E-LINE PACKAGE-3

ZVNL120A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Zetex Semiconductors
package instruction	TO-92 COMPATIBLE, E-LINE PACKAGE-3
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	LOW THRESHOLD
Configuration	SINGLE
Minimum drain-source breakdown voltage	200 V
Maximum drain current (Abs) (ID)	0.18 A
Maximum drain current (ID)	0.18 A
Maximum drain-source on-resistance	10 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)	7 pF
JEDEC-95 code	TO-92
JESD-30 code	O-PBCY-W3
JESD-609 code	e3
Humidity sensitivity level	1
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	200 °C
Package body material	PLASTIC/EPOXY
Package shape	ROUND
Package form	CYLINDRICAL
Peak Reflow Temperature (Celsius)	260
Polarity/channel type	N-CHANNEL
Maximum power dissipation(Abs)	0.7 W
Certification status	Not Qualified
surface mount	NO
Terminal surface	Matte Tin (Sn)
Terminal form	WIRE
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
transistor applications	SWITCHING
Transistor component materials	SILICON
Base Number Matches	1

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N-CHANNEL

ENHANCEMENT

L

MODE VERTICAL DMOS FET

ISSUE 2- MARCH 94

FEATURES

*

*R

*

ZVNL120A

!

2oovoltvD~

l)S(m)=lOi’

4

/

Lowthreshold

~}~

f

GS

handsets

APPLICATIONS

*

Telephone

n

~

E-Line

T092Compatible

1

ABSOLUTE MAXIMUM

RATINGS.

=~

Continuous

Drain Current at Tamb=250C

I

Pulsed Drain Current

Gate Source Voltage

Power Dissipation

:-:”

-----:::*::

Range+---l--5::Ti””-”+:-

”t::=:I:i-::d

__

at T ~mb=250C

Operating

and Storage —

Temperature

ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).

PARAMETER

SYMBCJL

MIN.

200

MAX.

–

UNIT

$

Drain-Soul-cc

Voltage

Gate-Source

Gate-Body

Breakdown

‘VDSS

v

ID=l mA, VG~=OV

“~””

‘-

‘-”-”

lD=lmA,

‘-

‘----F--

vG#

VDs

VGs

“-””

CONDITIONS.

Threshold

Leakage

Voltage

‘GS(th)

lGSS

0.5

_

l.5–

,o~:~

20V, vD~=ov

Zerc! Gate Voltage

Drain Current

l~ss

10

100

500

10

[:

Ds= f30V, vG-~OV,

T=125”C(2)

I :“=Fv:v::o-–-””_

+—.

—

—-–-—– —-——

“‘–

On-State

D;;n

Cur~ent(l)

On-State

——

lD(on)

;;A-~~::2~,7G;’;V——-

i)

.--.—

Static Drain-Source

Resistance (1

I

‘DS(on

..-

9fs

..—

Forward Transconductance

(1)(2)

(2)

10

200

85

()

mS

VGS=5V,lD=250rnA

VG~=3V, lD=125mA

VDS=25V,lD=250mA

—-

lnp~it Capacitance

c;.,

co,,

c;.,

;_

‘d(on)

t,

.—

‘d(off)

tf

pF

VDS==25 V, VGsOV,

f=l MHz

Common Source Output

Capacitance (2)

Reverse Transfer

Capacitan;;(2)

20

7

Turn-On

Time (2)(3)

-.

Rise Time (2)(3)

..—. —

Turn-Off Delay Time (2)(3)

Fall ;Ime

(1) Measured

(3) Switchinq

(2)(3)

:

Delay

/

,f

8

-’-..””-

ns

pF

—

.—

——.

VDD=25V,

~

lD=250mA

20

72

n; ‘-”

under pulsed conditions. Width= 300ps. Duty cycle <2% (2) Sample test.

times measured with 50Q souce impedance and <5r]s rise time on a pulse generator

3-401

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