DJLXT972MLC.A4 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> DJLXT972MLC.A4

DJLXT972MLC.A4: DescriptionDATACOM, ETHERNET TRANSCEIVER, PQFP48; CategoryWireless rf/communication Telecom circuit; File Size659KB，92 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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DJLXT972MLC.A4 Overview

DATACOM, ETHERNET TRANSCEIVER, PQFP48

DJLXT972MLC.A4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
Parts packaging code	QFP
package instruction	ROHS COMPLIANT, LQFP-48
Contacts	48
Reach Compliance Code	unknow
data rate	100000 Mbps
JESD-30 code	S-PQFP-G48
length	7 mm
Number of functions	1
Number of terminals	48
Transceiver quantity	1
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP48,.35SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.11 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm

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Intel

LXT972M Single-Port 10/100 Mbps

PHY Transceiver

Datasheet

The Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast

Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It

provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access

Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.

Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is

powered from a single 3.3V power supply.

Applications

■

Combination 10BASE-T/100BASE-TX

Network Interface Cards (NICs)

Wireless access points

Network printers

■

10/100 Personal Computer Memory Card

International Association (PCMCIA) cards

Cable Modems and Set-Top Boxes

Product Features

■

3.3V Operation

IEEE 802.3-compliant 10BASE-T or

100BASE-TX with integrated filters

Auto-negotiation and parallel detection

MII interface with extended register

capability

Robust baseline wander correction

■

Carrier Sense Multiple Access / Collision

Detection (CSMA/CD) or full-duplex

operation

JTAG boundary scan

MDIO serial port or hardware pin

configurable

Integrated, programmable LED drivers

48-pin Low-profile Quad Flat Package

RESET_L

ADDR[1:0]

MDIO

MDC

Management /

Mode Select

Logic

Power Supply

Clock

Generator

VCC

GND

REFCLK/XI

TX_EN

TXD[3:0]

TX PCS

Manchester

Encoder

Parallel/Serial

Converter

Scrambler

100

& Encoder

Auto

Negotiation

Set

OSP

Pulse

Shaper

Driver

TP Out

TPOP

TPON

TX_CLK

LED/CFG[3:1]

JTAG

COL

Collision

Detect

Clock

Generator

Media

Select

OSP

Adaptive EQ with

Baseline Wander

Cancellation

100TX

TDI

TDO

TMS

TCK

TRST_L

TP In

TPIP

TPIN

RX_CLK

RXD[3:0]

RX P CS

RX_DV

CRS

RX_ER

Serial-to-

Parallel

Carrier Sense Converter

Data Valid

Error Detect

100

Manchester

Decoder

Decoder &

Descrambler

OSP

Slicer

10BT

B3387-13

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

Contents

1.0

Introduction to This Document ......................................................................................... 10

1.1

1.2

2.0

3.0

4.0

5.0

Document Overview ............................................................................................10

Related Documents............................................................................................. 10

Block Diagram for Intel

LXT972M Transceiver............................................................... 11

Pin Assignments for Intel

LXT972M Transceiver ...........................................................12

Signal Descriptions for Intel

LXT972M Transceiver ....................................................... 15

Functional Description...................................................................................................... 21

5.1

Device Overview .................................................................................................22

5.1.1 Comprehensive Functionality ................................................................. 22

5.1.2 Optimal Signal Processing Architecture ................................................. 22

Network Media / Protocol Support.......................................................................23

5.2.1 10/100 Network Interface .......................................................................23

5.2.2 MII Data Interface ................................................................................... 25

5.2.3 Configuration Management Interface ..................................................... 25

Operating Requirements .....................................................................................28

5.3.1 Power Requirements ..............................................................................28

5.3.2 Clock Requirements ............................................................................... 28

Initialization.......................................................................................................... 29

5.4.1 MDIO Control Mode and Hardware Control Mode .................................31

5.4.2 Reduced-Power Modes .......................................................................... 31

5.4.3 Reset for Intel

LXT972M Transceiver................................................... 31

5.4.4 Hardware Configuration Settings ...........................................................33

Establishing Link .................................................................................................34

5.5.1 Auto-Negotiation.....................................................................................34

5.5.2 Parallel Detection ................................................................................... 35

MII Operation....................................................................................................... 36

5.6.1 MII Clocks............................................................................................... 37

5.6.2 Transmit Enable .....................................................................................38

5.6.3 Receive Data Valid ................................................................................. 38

5.6.4 Carrier Sense ......................................................................................... 39

5.6.5 Error Signals........................................................................................... 39

5.6.6 Collision .................................................................................................. 39

5.6.7 Loopback................................................................................................ 40

100 Mbps Operation ............................................................................................41

5.7.1 100BASE-X Network Operations ...........................................................41

5.7.2 Collision Indication ................................................................................. 44

5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 45

10 Mbps Operation.............................................................................................. 50

5.8.1 10BASE-T Preamble Handling ............................................................... 50

5.8.2 10BASE-T Carrier Sense .......................................................................50

5.8.3 10BASE-T Dribble Bits ........................................................................... 50

5.8.4 10BASE-T Link Integrity Test ................................................................. 51

5.8.5 Link Failure ............................................................................................. 51

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Intel

LXT972M Single-Port 10/100 Mbps PHY Transceiver

5.9

5.10

5.8.6 10BASE-T SQE (Heartbeat) .................................................................. 51

5.8.7 10BASE-T Jabber .................................................................................. 51

5.8.8 10BASE-T Polarity Correction................................................................ 51

Monitoring Operations ......................................................................................... 52

5.9.1 Monitoring Auto-Negotiation................................................................... 52

5.9.2 Monitoring Next Page Exchange............................................................ 52

5.9.3 LED Functions........................................................................................ 53

5.9.4 LED Pulse Stretching ............................................................................. 54

Boundary Scan (JTAG 1149.1) Functions .......................................................... 55

5.10.1 Boundary Scan Interface........................................................................ 55

5.10.2 State Machine ........................................................................................ 55

5.10.3 Instruction Register ................................................................................ 55

5.10.4 Boundary Scan Register ........................................................................ 56

5.10.5 Device ID Register ................................................................................. 56

6.0

Application Information..................................................................................................... 57

6.1

6.2

Magnetics Information ......................................................................................... 57

Typical Twisted-Pair Interface ............................................................................. 57

7.0

Electrical Specifications ................................................................................................... 61

7.1

7.2

Electrical Parameters .......................................................................................... 61

Timing Diagrams ................................................................................................. 65

8.0

9.0

10.0

Intel

LXT972M Transceiver Package Specifications...................................................... 90

10.1

Top Label Markings............................................................................................. 91

11.0

Product Ordering Information ........................................................................................... 92

Figures

Intel

LXT972M Transceiver Block Diagram....................................................... 11

Pin Assignments for Intel

LXT972M Transceiver 48-Pin LQFP Package ......... 12

Management Interface Read Frame Structure ................................................... 27

Management Interface Write Frame Structure ................................................... 27

Initialization Sequence for Intel

LXT972M Transceiver ..................................... 30

Link Establishment Overview) ............................................................................. 34

Clocking for 10BASE-T ...................................................................................... 37

Clocking for 100BASE-X .................................................................................... 37

Clocking for Link Down Clock Transition ............................................................ 38

Intel

LXT972M Transceiver Loopback Paths .................................................... 40

100BASE-X Frame Format ................................................................................ 41

100BASE-TX Data Path ..................................................................................... 42

100BASE-TX Reception with No Errors ............................................................. 43

100BASE-TX Reception with Invalid Symbol ..................................................... 43

100BASE-TX Transmission with No Errors ........................................................ 44

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

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