51762-10313600CB datasheet, PDF

51762-10313600CB: DescriptionBoard Connector, 139 Contact(s), 4 Row(s), Female, Right Angle, Press Fit Terminal, Guide Pin, Receptacle; CategoryThe connector The connector; File Size253KB，3 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

51762-10313600CB Overview

Board Connector, 139 Contact(s), 4 Row(s), Female, Right Angle, Press Fit Terminal, Guide Pin, Receptacle

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Amphenol
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	TERMINAL PITCH FOR POWER CONTACTS: 6.35 MM
Board mount options	HOLE .125-.137
body width	0.47 inch
subject depth	0.82 inch
body length	4.8 inch
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	GOLD (30) OVER NICKEL (50)
Contact completed and terminated	TIN LEAD (100) OVER NICKEL (50)
Contact point gender	FEMALE
Contact material	COPPER ALLOY
Contact resistance	2 mΩ
Contact style	BLADE PIN-SKT
DIN compliance	NO
Durability	200 Cycles
Filter function	NO
IEC compliance	NO
maximum insertion force	.973 N
Insulation resistance	10000000000 Ω
insulator material	GLASS FILLED THERMOPLASTIC
JESD-609 code	e0
MIL compliance	NO
Manufacturer's serial number	51762
Mixed contacts	YES
Installation option 1	GUIDE PIN
Installation option 2	LOCKING
Installation method	RIGHT ANGLE
Installation type	BOARD
Number of connectors	ONE
Number of rows loaded	4
Maximum operating temperature	105 °C
Minimum operating temperature	-20 °C
Options	GENERAL PURPOSE
Plating thickness	30u inch
Guideline	UL
reliability	COMMERCIAL
Terminal length	0.154 inch
Terminal pitch	2.54 mm
Termination type	PRESS FIT
Total number of contacts	139
UL Flammability Code	94V-0
Evacuation force-minimum value	.17792 N
Base Number Matches	1

PDM: Rev:K

STATUS:

Released

Printed: Dec 20, 2010

[I contribute to the Xilinx Resource Center] A large amount of Verilog source code: A lot of Verilog source codeVerilog HDL 程序举例一，基本组合逻辑功能：双向管脚（clocked bidirectional pin） Verilog HDL: Bidirectional PinThis example implements a clocked bidirectional pin in Verilog HDL. The value of ...; wanghongyang FPGA/CPLD

Slow display speed: Why does the display speed slow down after I turn on the "average sampling" mode or set a longer persistence time when using Dingyang oscilloscope?...; lily608487 Test/Measurement

Scattered: Can ITU656 data without VSYNC/HREF trigger the CAMERA interrupt of S3C6410?: Can ITU656 data without VSYNC/HREF trigger the S3C6410 CAMERA interrupt? How to configure the S3C6410 CAMERA interface? What are the requirements for the CAMERA input? Can it be the standard 720*576 P...; eekingking Embedded System

My Beaglebone learning journey: Organize the previous posts and make a general post to facilitate communication.1. BeagleBone Hardware Performance Test_Weekly Planhttps://bbs.eeworld.com.cn/thread-324885-1-1.html 2. BeagleBone hardw...; chenzhufly DSP and ARM Processors

How to solve the glitch: [font=黑体][size=5]vcc is a fixed level I set, q1 is a sine wave generated by counter + rom, alb is the output waveform after vcc and q1 pass through the comparator, q1 No code? How to solve the glitch...; xmllf FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components