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COREU1LL-AR

Description
CoreU1LL UTOPIA Level 1 Link-Layer Interface
File Size73KB,8 Pages
ManufacturerActel
Websitehttp://www.actel.com/
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COREU1LL-AR Overview

CoreU1LL UTOPIA Level 1 Link-Layer Interface

CoreU1LL UTOPIA Level 1 Link-Layer Interface
Product Summary
IDE and Industry Standard Synthesis and
Simulation Tools
RTL Version
– VHDL Source Code
– Core Synthesis and Simulation Scripts
Actel-Developed
Testbench
(VHDL)
Fully
Supported by Industry-Standard Simulation Tools
Intended Use
Standard UTOPIA Level 1 Interface to any ATM
PHY-Layer Device
Key Features
Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer
(Master) Interface Complies with the ATM Forum
UTOPIA Specification, Level 1 Version 2.01 (af-phy-
0017.000)
Separate Tx and Rx Clocks and Interface Pins
Supports Cell-Level Handshake for 53- or 54-byte
ATM Cells with Automatic Add/Drop of the UDF2
Field in the ATM Header in 53-byte Mode
16-Bit (54-byte) User Interfaces can be Used
Directly or Bolt-Up to One of Actel's ATM Cell
Buffer Blocks: ATMBUFx
Design Tools Support
Simulation: VITAL-Compliant VHDL and OVI-
Compliant Verilog Simulators
Synthesis: LeonardoSpectrum
TM
, Synplify
®
, Design
Compiler
®
, FPGA Compiler
TM
, and FPGA Express
TM
Contents
General Description ...................................................
Device Requirements .................................................
UTOPIA Interface .......................................................
User Interface .............................................................
Ordering Information ................................................
List of Changes ...........................................................
Datasheet Categories .................................................
1
2
2
3
6
7
7
Supported Families
Fusion
ProASIC3/E
ProASIC
PLUS®
Axcelerator
®
Core Deliverables
Netlist Version
– Compiled RTL Simulation Model Fully
Supported in the Actel Libero
®
Integrated
Design Environment (IDE)
– Structural VHDL and Verilog Netlists (with and
without I/O Pads) Compatible with Actel Libero
General Description
CoreU1LL is a UTOPIA Level 1 Link-Layer (Master)
interface core that connects directly to any ATM PHY-
Layer (Slave) device and user logic (or optional ATM cell
buffer blocks) to provide an interface between the PHY-
Layer device and a non-standard Link-Layer device or
user logic (Figure
1).
RX
Utopia
Level 1
PHY-Layer
Device
CoreATMBUF3
TX
CoreU1LL
CoreATMBUF3
User
Logic
Other
Device
Figure 1 •
Block Diagram
December 2005
© 2005 Actel Corporation
v 4 .0
1

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