Functionally compatible with traditional asynchronous
SRAMs
Equal address and chip-enable access times
HiRel temperature range (-40
o
C to +105
o
C)
Automatic data protection with low-voltage inhibit
circuitry to prevent writes on power loss
CMOS and TTL compatible
Data non-volatile for > 20 years at temperature
Read/Write endurance: 1E14 cycles
64-pin ceramic flatpack package
Operational environment:
- Total dose: 1 Mrad(Si)
- SEL Immune: 112 MeV-cm
2
/mg @125
o
C
- SEU Immune: Memory Cell 112 MeV-cm
2
/mg @25
o
C
Standard Microelectronics Drawing (SMD) - 5962-13207
- QML Q, Q+, and V pending
INTRODUCTION
The Aeroflex 64Megabit Non-Volatile magnetoresistive
random access memory (MRAM) is a high-performance
memory multichip module (MCM) compatible with traditional
asynchronous SRAM operations, organized as four individual
16,777,216 words by 8 bits.
The MRAM is equipped with five chip enables (/En), a single
write enable (/W), and a single output enable (/G) pins, allowing
for significant system design flexibility without bus contention.
Data is non-volatile for > 20 years at temperature and data is
automatically protected against power loss by a low voltage
write inhibit.
Figure 1. UT8MR8M8 MRAM Block Diagram
1
DEVICE OPERATION
VSS
VDD
VSS
VSS
/E0
A4
A3
A2
A1
A0
A19
ZZ/RST
NUO
DQ4
DQ5
VDD
VSS
DQ6
DQ7
/E1
/E_All
A21
A22
A9
A8
A7
A6
A5
VSS
VSS
VSS
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
VSS
VSS
/E3
A20
A15
A16
A17
A18
VSS
/G
VSS
DQ3
DQ2
VSS
VDD
DQ1
DQ0
/E2
VSS
MBE
/W
A10
A11
A12
A13
A14
VSS
VSS
VDD
VSS
The UT8MR8M8 has control inputs called Chip Enable
(/E[3:0]), Chip Enable All (/E_ALL), Write Enable (/W),
Output Enable (/G), and sleep/reset mode (ZZ/RST); 23
address inputs, A[22:0]; eight bidirectional data lines,
DQ[7:0]; and a Multi-bit Error Flag (MBE). /E[3:0] controls
device selection, active, and standby modes. Asserting /E[3:0]
enables the device, causes IDD to rise to its active value, and
decodes the 21 address inputs, A[20:0], to select one of
16,777,216 words in the memory.
Note:
Only one Chip Enable
may be active at any time. Asserting /E_ALL allows the
device to be addressed as a single, 64Mb memory using
address bits A21 and A22 to decode and select 1 of 4 MRAM
die. /W controls read and write operation. During a read cycle,
/G must be asserted to enable the outputs. ZZ/RST controls the
sleep/reset mode operation and provides device reset
capability. Enabling sleep/reset mode causes all other inputs to
be don't cares. ZZ/RST places all die into internal low power
even while system power is still applied to V
DD
. The MBE pin
is an open drain in which when pulled down, it identifies that
ECC logic has detected two bit errors during the current read
cycle. It allows for wired-or of multiple MBE when using
multiple MRAMs.
Table 2. Chip Enable Functions Table
/E_ALL /E_0 /E_1 /E_2 /E_3 A22 A21 Comment
0
1
1
1
1
0
0 MRAM Die 0
Enabled
0
1
1
1
1
0
1 MRAM Die 1
Enabled
0
1
1
1
1
1
0 MRAM Die 3
Enabled
0
1
1
1
1
1
1 MRAM Die 2
Enabled
1
0
1
1
1
X
X MRAM Die 0
Enabled
1
1
0
1
1
X
X MRAM Die 1
Enabled
1
1
1
0
1
X
X MRAM Die 2
Enabled
1
1
1
1
0
X
X MRAM Die 3
Enabled
*Note:
Only one /E[3:0] pin may be active at any time.
Figure 2. 40ns MRAM Pinout (64)
PIN NAMES
Table 1. 8M x 8 Pin Functions
Signal Name
A[22:0]
/E[3:0]
1
/E_All
/W
/G
DQ[7:0]
VDD
VSS
ZZ/RST
MBE
2
NUO
Function
Address Input
Chip Enable
Chip Enable All
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Deep Power Down/Reset
Multi-Bit Error Flag
Not used output
Do not connect
Driven internally
2
Table 3. Device Operation Truth Table
ZZ/
RST
H
L
/E[3:0]
*
X
H
/G
X
X
/W
X
X
Mode
Deep Sleep/
Reset Mode
Not
Selected
Output
Disabled
Byte Read
Byte Write
VDD
DQ[7:0]
Current
Q
IZZ
Q
IDD
I
DDR
I
DDR
I
DDW
HI-Z
HI-Z
L
L
L
L
L
L
H
L
X
H
H
L
HI-Z
D
OUT
D
IN
*Notes:
1.Only one /E[3:0] pin may be active at any time.
2. MBE pin is not functionally tested for prototypes.
*Note:
Only one /E[3:0] pin may be active at any time.
READ CYCLE
A combination of /W greater than V
IH
(min) and a single /En
less than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of chip enable, output enable, or valid
address to valid data output.
MRAM Read Cycle 1, the Address Access in Figure 4a, is
initiated by a change in address inputs after a single /En is
asserted, /G asserted and /W deasserted. Valid data appears on
data outputs DQ[7:0] after the specified t
AVQV
is satisfied.
Outputs remain active throughout the entire cycle. As long as
a single chip enable and output enable are active, the address
inputs may change at a rate equal to the minimum read cycle
time (t
AVAV
).
MRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 4b, is initiated by a single /En going active while /G
remains asserted, /W remains deasserted, and the addresses
remain stable for the entire cycle. After the specified t
ELQV
is
satisfied, the eight-bit word addressed by A[20:0] is accessed
and appears at the data outputs DQ[7:0].
WRITE CYCLE
A combination of /W and a single /En less than V
IL
(max)
defines a write cycle. The state of /G is a “don’t care” for a
write cycle. The outputs are placed in the high-impedance state
when either /G is greater than V
IH
(min), or when /W is less
than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
5a, is defined by a write terminated by /W going high, with a
single /En still active. The write pulse width is defined by
t
WLWH
when the write is initiated by /W, and by t
ETWH
when
the write is initiated by a single /En. Unless the outputs have
been previously placed in the high-impedance state by /G, the
user must wait t
WLQZ
before applying data to the nine
bidirectional pins DQ[7:0] to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in
Figure 5b, is defined by a write terminated by a single /En going
inactive. The write pulse
width is defined by t
WLEH
when the write is initiated
by /W, and by t
ELEH
when
the write is initiated by a
single /En going active.
For the /W initiated write,
unless the outputs have
been previously placed in
the high-impedance state
by /G, the user must wait
t
WLQZ
before applying
data to the eight
bidirectional pins DQ[7:0] to avoid bus contention.
OPERATIONAL ENVIRONMENT
The UT8MR8M8 MRAM incorporates special design and
layout features which allows operation in harsh environments.
Table 4. Operational Environment
Design Specifications
PARAMETER
TID
SEL Immunity
1
SEU Memory Cell
Immunity
2
Notes:
1. SEL test performed at V
DD
= 3.6V and temperature = 125
o
C.
2. SEU test performed at V
DD
= 3.0V and unpowered at room temperature.
LIMIT
1
< 112
< 112
UNITS
Mrad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
POWER UP AND POWER DOWN SEQUENCING
The MRAM is protected from write operations whenever
V
DD
is less than V
WI
. As soon as V
DD
exceeds V
DD
(min),
there is a startup time of 2 ms before read or write operations
can start. This time allows memory power supplies to
stabilize. The /En and /W control signals should track V
DD
on
power up to V
DD
- 0.2 V or V
IH
(whichever is lower) and
remain high for the startup time. In most systems, this means
that these signals should be pulled up with a resistor so the
signal remains high if the driving signal is Hi-Z during power
up. Any logic that drives /En and /W should hold the signals
high with a power-on reset signal for longer than the startup
time. During power loss or brownout where V
DD
goes below
V
WI
, writes are protected and a startup time must be observed
when power returns above V
DD
(min).
The MRAM supports sleep/reset mode operation using the
ZZ/RST control pin. To enter sleep mode/reset, ZZ/RST
must be pulled high. The device will enter sleep/reset mode
within 40ns. In order to exit sleep/reset mode, /En and /W
must be high before ZZ/
RST is pulled low. As
soon as ZZ/RST is driven
low, the user must allow
100us before performing
any other operation in
order for the device to
properly initialize. Aero-
flex strongly recommends
reseting the device during
system power-up.
Figure 3. UT8MR8M8 Power Up and Power Down Sequencing Diagram
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
The device contains protection against magnetic fields. Precautions should be taken to avoid device exposure of any magnetic field
intensity greater than specified.
SYMBOL
V
DD
V
IN
I
IO
P
D
T
J
JC
T
STG
ESD
HBM
H
max_write
H
max_read
Supply Voltage
2
Voltage on any pin
2
DC I/O current per pin @ T
J
= 125° for 20yrs
Package power dissipation
3
Maximum junction temperature
Thermal resistance junction to case – Single Die
Storage temperature
ESD
Maximum magnetic field during write
Maximum magnetic field during read or standby
PARAMETER
VALUE
-0.5 to 4.0
-0.5 to V
DD
+0.5
±
20
0.600
+125
5
-65 to +125
>2000
5000
8000
o
UNIT
V
V
mA
W
o
C
C/W
o
C
V
A/m
A/m
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions.
Exposure to excessive voltages or magnetic fields could affect device reliability.
2. All voltages are referenced to V
SS
.
3. Power dissipation capability depends on package characteristics and use environment.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
T
C
V
DD
V
WI
V
IH
V
IL
PARAMETER
Operating case temperature
Operating supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
LIMITS
-40
o
C to +105
o
C
3.0V to 3.6V
2.5V to 3.0V
1
2.2V to V
DD
+0.3V
V
SS
-0.3V to 0.8V
Notes:
1. After power up or if V
DD
falls below V
WI
, a waiting period of 2 ms must be observed, and /En and /W must remain high for 2 ms. Memory is designed to prevent
writing for all input pin conditions if V
DD
falls below minimum V
WI
.
4
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
V
DD
= 3.0V to 3.6V; Unless otherwise noted, Tc is per the temperature ordered
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IO1
I
IN
I
INZZ
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Input leakage current ZZ/RST
Three-state output leakage
current
I
OL
= 4mA,V
DD
=V
DD
(min)
I
OL
= + 100A,V
DD
=V
DD
(min)
I
OH
= -4mA,V
DD
=V
DD
(min)
I
OH
= -100A,V
DD
=V
DD
(min)
= 1MHz @ 0V
= 1MHz @ 0V
V
IN
= V
DD
and V
SS
V
IN
= V
DD
and V
SS
V
O
= V
DD
and V
SS,
V
DD
= V
DD
(max)
/G = V
DD
(max)
V
DD
= V
DD
(max), V
O
= V
DD
V
DD
= V
DD
(max), V
O
= V
SS
Read mode
(I
OUT
= 0mA; V
DD
= max)
Write mode
(V
DD
= max)
CMOS leakage current
(/E = V
DD
; all other inputs equal
V
SS
or V
DD
; V
DD
= max)
CMOS leakage current
(/E = V
DD
; all other inputs equal
V
SS
or V
DD
; V
DD
= max)
-40
o
C
+25
o
C
+105
o
C
Q
IZZ4
Deep power down and reset
supply current
TBD
40
mA
A
-1
-1
2.4
V
DD
-0.2
TBD
TBD
+1
TBD
+1
CONDITION
MIN
2.2
0.8
0.4
V
SS
+0.2
MAX
UNIT
V
V
V
V
V
V
pF
pF
A
A
A
I
OS2, 3
I
DDR
I
DDW
Q
IDD
Short-circuit output current
-100
+100
mA
Active read supply current
100
mA
Active write supply current
170
mA
Quiescent supply current
26
mA
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Allow 100s to exit sleep/reset mode before performing any other operation.
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