REVISIONS
LTR
F
G
DESCRIPTION
Changes in accordance with NOR 5962-R040-95.
Redrawn with changes. Add device types 39 and 40. Add vendor
CAGE 66301 and 0EU86 as sources of supply for device types 39
and 40. Add case 7. Add vendor CAGE 0EU86 as source of supply
for case 7. Convert document to updated SMD boilerplate. Editorial
changes throughout.
Add device type 41. Make corrections to case outline N, dimension b.
Add vendor CAGE 65786 as source of supply for device type 41.
Update boilerplate. Editorial changes throughout.
Add device types 42, 43, 44, 45, and 46. Editorial changes to pages
1, 3, 7-15. Update boilerplate. ksr
Added provisions to accommodate radiation-hardened devices.
Added device type 47 to drawing. glg
Corrected case outline 8 Figure 1 to show correct numbering of
terminals. Corrected Figure 2 Terminal connections. Corrected the
case outline Y Figure 1 to show the proper distance of E and E1.
Added note to Case outline Y Figure 1, to allow for bottom brazed
package as an alternative style to the side brazed package . Update
boilerplate. Editorial changes throughout. ksr
DATE (YR-MO-DA)
94-12-08
96-03-20
APPROVED
M. A. Frye
M. A. Frye
H
97-03-26
Raymond Monnin
J
98-03-03
Raymond Monnin
K
00-03-01
Raymond Monnin
L
00-12-08
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
L
35
L
15
L
36
L
16
L
37
L
17
L
38
L
18
REV
L
39
L
19
L
40
L
20
L
41
L
21
L
1
L
42
L
22
L
2
L
43
L
23
L
3
L
44
L
24
L
4
L
45
L
25
L
5
L
46
L
26
L
6
L
47
L
27
L
7
L
48
L
28
L
8
L
49
L
29
L
9
L
50
L
30
L
10
L
51
L
31
L
11
L
52
L
32
L
12
L
33
L
13
L
34
L
14
SHEET
PREPARED BY
Kenneth S. Rice
CHECKED BY
Raymond Monnin
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
89-04-21
REVISION LEVEL
L
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 128K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM) LOW POWER,
MONOLITHIC SILICON
SIZE
A
SHEET
1 OF
52
5962-E233-00
CAGE CODE
67264
5962-89598
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q
and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in
the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected
in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
Federal
stock class
designator
\
~
~
~
-
RHA
designator
(see 1.2.1)
/
\/
Drawing number
~
~
~
89598
01
Device
type
(see 1.2.2)
~
~
~
M
Device
class
designator
(see 1.2.3)
~
~
~
Case
outline
(see 1.2.4)
~
~
~
X
Lead
finish
(see 1.2.5)
~
~
~
A
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix
A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Generic number 1/
Circuit function
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM dual CE
Access time
120 ns
100 ns
85 ns
70 ns
120 ns
100 ns
85 ns
70 ns
55 ns
45 ns
35 ns
25 ns
120 ns
100 ns
85 ns
70 ns
55 ns
45 ns
35 ns
25 ns
20 ns
120 ns
100 ns
85 ns
70 ns
55 ns
45 ns
35 ns
25 ns
120 ns
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document
and will also be listed in MIL-HDBK-103.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-89598
SHEET
L
2
Device type
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Generic number 1/
Circuit function
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM
128K x 8 low power CMOS SRAM
128K x 8 standard power CMOS SRAM dual CE
128K x 8 low power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM
128K x 8 standard power CMOS SRAM dual CE
128K x 8 standard power CMOS SRAM
128K x 8 very low power CMOS SRAM
Access time
100 ns
85 ns
70 ns
55 ns
45 ns
35 ns
25 ns
20 ns
20 ns
20 ns
15 ns
70 ns
70 ns
15 ns
12 ns
12 ns
30 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
U
T
N
M
9
8
7
2/
Descriptive designator
GDIP1-T32 or CDIP2-T32
See figure 1
See figure 1
See figure 1
See figure 1
See figure 1
CQCC1-N32
See figure 1
See figure 1
See figure 1
Terminals
32
32
32
32
32
32
32
32
32
32
Package style
dual-in-line
SOJ package
dual-in-line
rectangular chip carrier
flat pack
rectangular chip carrier
rectangular chip carrier
J-leaded rectangular chip carrier
zig-zag in-line
SOJ package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 3/ 4/
Supply voltage range (VCC) ........................................
DC input voltage range (V IN) .......................................
DC output voltage range (VOUT).................................
Storage temperature range..........................................
Maximum power dissipation (PD) ................................
Lead temperature (soldering, 10 seconds) ..................
-0.5 V dc to +7.0 V dc
-0.5 V dc to VCC+0.5 V dc 5/
-0.5 V dc to VCC+0.5 V dc 5/
-65
q
C to +150
q
C
1.0 W
+260
q
C
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document
and will also be listed in MIL-HDBK-103.
2/ A bottom brazed option for this package now exists (See figure 1, case outline Y NOTE:). Customers may specify in the
purchase order to negate the option as acceptable for their use.
3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
4/ All voltages referenced to VSS (VSS = ground) unless otherwise specified.
5/ Negative undershoots to a minimum of -3.0 V are allowed with a maximum of 20 ns pulse width.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-89598
SHEET
L
3
1.3 Absolute maximum ratings - continued. 3/ 4/
Thermal resistance, junction-to-case (
T
JC):
Case M.......................................................................
Cases X, Y, Z, U, and 7 .............................................
Cases T, N, and 9 ......................................................
Case 8........................................................................
Output voltage applied in high Z state .........................
Maximum power dissipation, (PD) ...............................
Maximum junction temperature (TJ) ............................
1.4 Recommended operating conditions.
Supply voltage range (VCC) ........................................
Supply voltage range (VSS).........................................
High level input voltage range (VIH) ............................
Low level input voltage range (VIL)..............................
Case operating temperature range (TC)......................
1.5 Logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) .............. 8/ percent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those
listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto,
cited in the solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-973 - Configuration Management.
MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
4/ All voltages referenced to VSS (VSS = ground) unless otherwise specified.
6/ When the
T
JC for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein.
7/ Maximum junction temperature may be increased to +175
q
C during burn-in and steady-state life.
8/ When a value is determined per customer requirements, it shall be provided.
4.5 V dc minimum to 5.5 V dc maximum
0.0 V dc
2.2 V dc to VCC + 0.5 V dc
-0.5 V dc to 0.8 V dc
-55
q
C to +125
q
C
See MIL-STD-1835
11
q
C/W 6/
10
q
C/W 6/
16
q
C/W 6/
-0.5 V dc to VCC+0.5 V dc
1.0 W
+150
q
C 7/
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-89598
SHEET
L
4
2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192M-95
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to the American Society for Testing and Materials,
1916 Race Street, Philadelphia, PA 19103.)
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD 78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington,
VA 22201.)
(Non-Government standards and other publications are normally available from the organizations that prepare or
distribute the documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations
unless a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device
class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the
manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V
alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in
accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.
3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection
only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and
pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water
vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the
requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-89598
SHEET
L
5
Embedded System
京公网安备 11010802033920号
EEWORLD
