74LVC2G240-Q100
Dual inverting buffer/line driver; 3-state
Rev. 1 — 15 October 2014
Product data sheet
1. General description
The 74LVC2G240-Q100 is a dual inverting buffer/line driver with 3-state outputs. The
output enable inputs 1OE and 2OE, control the 3-state outputs. A HIGH level at pins nOE
causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all
inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G240-Q100 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing a damaging backflow current through the device when it is
powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
NXP Semiconductors
74LVC2G240-Q100
Dual inverting buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC2G240DP-Q100
74LVC2G240DC-Q100
40 C
to +125
C
40 C
to +125
C
Name
Description
Version
TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
V240
V40
Type number
74LVC2G240DP-Q100
74LVC2G240DC-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
EN
1OE
1A
2OE
2A
2Y
1Y
EN
001aah782
001aah783
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC2G240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 15 October 2014
2 of 15
NXP Semiconductors
74LVC2G240-Q100
Dual inverting buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
Fig 3.
Pin configuration SOT505-2 and SOT765-1
6.2 Pin description
Table 3.
Symbol
1OE
1A
2Y
GND
2A
1Y
2OE
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
output enable input 1OE (active LOW)
data input
data output
ground (0 V)
data input
data output
output enable input 2OE (active LOW)
supply voltage
7. Functional description
Table 4.
Input
nOE
L
L
H
[1]
Function table
[1]
Output
nA
L
H
X
nY
H
L
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC2G240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 15 October 2014
3 of 15
NXP Semiconductors
74LVC2G240-Q100
Dual inverting buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
Enable mode
Disable mode
Power-down mode
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[1]
[1]
[1][2]
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
0.5
0.5
0.5
-
-
100
65
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
+6.5
50
100
-
+150
300
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
40 C
to +125
C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 packages: above 55
C
the value of P
tot
derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly at 8.0 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
Operating conditions
Parameter
supply voltage
input voltage
output voltage
V
CC
= 1.65 V to 5.5 V;
Enable mode
V
CC
= 1.65 V to 5.5 V;
Disable mode
V
CC
= 0 V; Power-down mode
T
amb
t/V
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Conditions
Min
1.65
0
0
0
0
40
-
-
Max
5.5
5.5
V
CC
5.5
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVC2G240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 15 October 2014
4 of 15
NXP Semiconductors
74LVC2G240-Q100
Dual inverting buffer/line driver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
V
OH
HIGH-level output voltage V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
I
CC
I
CC
C
I
input leakage current
OFF-state output current
power-off leakage current
supply current
additional supply current
input capacitance
V
I
= 5.5 V or GND; V
CC
= 0 V to 5.5 V
V
I
= V
IH
or V
IL
; V
O
= 5.5 V or GND;
V
CC
= 3.6 V
V
I
or V
O
= 5.5 V; V
CC
= 0 V
V
I
= 5.5 V or GND; I
O
= 0 A;
V
CC
= 1.65 V to 5.5 V
per pin; V
I
= V
CC
0.6 V; I
O
= 0 A;
V
CC
= 2.3 V to 5.5 V
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.1
5
2
-
-
-
-
-
-
5
10
10
10
500
-
V
V
V
V
V
V
A
A
A
A
A
pF
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.45
0.3
0.4
0.55
0.55
V
V
V
V
V
V
0.65
V
CC
1.7
2.0
0.7
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.35
V
CC
0.7
0.8
0.3
V
CC
V
V
V
V
V
V
V
V
Conditions
Min
Typ
[1]
Max
Unit
74LVC2G240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 15 October 2014
5 of 15
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