MC74HC4060DT datasheet, PDF - EEWORLD Datasheet

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MC74HC4060DT: DescriptionBinary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up Direction, CMOS, PDSO16, PLASTIC, TSSOP-16; Categorylogic logic; File Size265KB，10 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC74HC4060DT Overview

Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up Direction, CMOS, PDSO16, PLASTIC, TSSOP-16

MC74HC4060DT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	TSSOP,
Reach Compliance Code	unknown
Other features	OUTPUTS FROM 10 STAGES AVAILABLE; BUILT-IN OSCILLATOR; OSCILLATOR DISABLED BY CLEAR INPUT
Counting direction	UP
series	HC/UH
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	5 mm
Load capacitance (CL)	50 pF
Load/preset input	NO
Logic integrated circuit type	BINARY COUNTER
Operating mode	ASYNCHRONOUS
Number of digits	14
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	480 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	4.4 mm
minfmax	17 MHz
Base Number Matches	1

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

14-Stage Binary Ripple

Counter with Oscillator

High–Performance Silicon–Gate CMOS

The MC54/74HC4060 is identical in pinout to the standard CMOS

MC14060B. The device inputs are compatible with standard CMOS outputs;

with pullup resistors, they are compatible with LSTTL outputs.

This device consists of 14 master–slave flip–flops and an oscillator with a

frequency that is controlled either by a crystal or by an RC circuit connected

externally. The output of each flip–flop feeds the next, and the frequency at

each output is half that of the preceding one. The state of the counter

advances on the negative–going edge of Osc In. The active–high Reset is

asynchronous and disables the oscillator to allow very low power consump-

tion during standby operation.

State changes of the Q outputs do not occur simultaneously because of

internal ripple delays. Therefore, decoded output signals are subject to

decoding spikes and may need to be gated with Osc Out 2 of the HC4060.

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 1

µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 390 FETs or 97.5 Equivalent Gates

MC54/74HC4060

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

ORDERING INFORMATION

MC54HCXXXXJ

MC74HCXXXXN

MC74HCXXXXDT

Ceramic

Plastic

TSSOP

PIN ASSIGNMENT

Q12

VCC

Q10

RESET

OSC IN

OSC OUT 1

OSC OUT 2

LOGIC DIAGRAM

OSC OUT 1

OSC OUT 2

OSC IN

PIN 16 = VCC

PIN 8 = GND

Q10

Q12

Q13

Q14

Clock

Q13

Q14

GND

FUNCTION TABLE

Reset

Output State

No Change

Advance to Next State

All Outputs are Low

RESET

10/95

Motorola, Inc. 1995

REV 6

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