CAT28LV65NA-30T datasheet, PDF

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CAT28LV65NA-30T: Description64K-Bit CMOS PARALLEL E2PROM; Categorystorage storage; File Size57KB，10 Pages; ManufacturerCatalyst; Websitehttp://www.catalyst-semiconductor.com/

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CAT28LV65NA-30T Overview

64K-Bit CMOS PARALLEL E2PROM

CAT28LV65NA-30T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Catalyst
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	300 ns
Other features	100000 PROGRAM/ERASE CYCLES; 100 YEAR DATA RETENTION
Data retention time - minimum	100
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	65536 bi
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.55 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.43 mm

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Preliminary

CAT28LV65

64K-Bit CMOS PARALLEL E

PROM

FEATURES

3.0V to 3.6V Supply

Read Access Times:

CMOS and TTL Compatible I/O

Automatic Page Write Operation:

– 250/300/350ns

Low Power CMOS Dissipation:

– 1 to 32 Bytes in 5ms

– Page Load Timer

End of Write Detection:

– Active: 8 mA Max.

– Standby: 100

A Max.

Simple Write Operation:

– On-Chip Address and Data Latches

– Self-Timed Write Cycle with Auto-Clear

Fast Write Cycle Time:

– Toggle Bit

–

DATA

Polling

– RDY/BUSY

BUSY

Hardware and Software Write Protection

100,000 Program/Erase Cycles

100 Year Data Retention

– 5ms Max.

Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT28LV65 is a low voltage, low power, CMOS

parallel E

PROM organized as 8K x 8-bits. It requires a

simple interface for in-system programming. On-chip

address and data latches, self-timed write cycle with

auto-clear and V

power up/down write protection

eliminate additional timing and protection hardware.

DATA

Polling, RDY/BUSY and Toggle status bit signal

the start and end of the self-timed write cycle. Addition-

ally, the CAT28LV65 features hardware and software

write protection.

The CAT28LV65 is manufactured using Catalyst’s ad-

vanced CMOS floating gate technology. It is designed to

endure 100,000 program/erase cycles and has a data

retention of 100 years. The device is available in JEDEC

approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-

pin PLCC packages.

BLOCK DIAGRAM

A5–A12

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

ROW

DECODER

8,192 x 8

PROM

ARRAY

32 BYTE PAGE

VCC

HIGH VOLTAGE

GENERATOR

CONTROL

LOGIC

I/O BUFFERS

TIMER

DATA POLLING,

RDY/BUSY &

TOGGLE BIT

COLUMN

DECODER

28LV65 F01

I/O0–I/O7

A0–A4

RDY/BUSY

ADDR. BUFFER

& LATCHES

Characteristics subject to change without notice

Doc. No. 25041-00 2/98

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