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CAT28C512T14-12T

Description
512K-Bit CMOS PARALLEL E2PROM
Categorystorage    storage   
File Size74KB,10 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT28C512T14-12T Overview

512K-Bit CMOS PARALLEL E2PROM

CAT28C512T14-12T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeTSOP
package instructionTSOP1, TSSOP40,.56,20
Contacts40
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time120 ns
Other features10000 PROGRAM/ERASE CYCLES; DATA RETENTION = 100 YEARS
command user interfaceNO
Data pollingYES
Data retention time - minimum100
Durability100000 Write/Erase Cycles
JESD-30 codeR-PDSO-G40
JESD-609 codee0
length12.4 mm
memory density524288 bi
Memory IC TypeEEPROM
memory width8
Humidity sensitivity level2A
Number of functions1
Number of terminals40
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Encapsulate equivalent codeTSSOP40,.56,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
page size128 words
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.0002 A
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
switch bitYES
width10 mm
Maximum write cycle time (tWC)5 ms
Base Number Matches1
Advanced
CAT28C512/513
512K-Bit CMOS PARALLEL E
2
PROM
FEATURES
s
Fast Read Access Times: 120/150 ns
s
Low Power CMOS Dissipation:
s
Automatic Page Write Operation:
–Active: 50 mA Max.
–Standby: 200
µ
A Max.
s
Simple Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s
End of Write Detection:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
–Toggle Bit
–DATA Polling
DATA
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial and Automotive
–5ms Max
s
CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel E
2
PROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
A7–A15
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
65,536 x 8
E
2
PROM
ARRAY
128 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5096 FHD F02
I/O0–I/O7
A0–A6
ADDR. BUFFER
& LATCHES
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
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