CAT28C256HN-12T datasheet, PDF

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CAT28C256HN-12T: Description5 Volt, Byte Alterable E2PROM; Categorystorage storage; File Size78KB，10 Pages; ManufacturerCatalyst; Websitehttp://www.catalyst-semiconductor.com/

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CAT28C256HN-12T Overview

5 Volt, Byte Alterable E2PROM

CAT28C256HN-12T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Catalyst
Parts packaging code	QFJ
package instruction	QCCJ,
Contacts	32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	120 ns
Other features	100000 PROGRAM/ERASE CYCLES
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	262144 bi
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	3.55 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.43 mm

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CAT28C256

32K-Bit Parallel E

PROM

FEATURES

Fast Read Access Times: 120/150ns

Low Power CMOS Dissipation:

Hardware and Software Write Protection

Automatic Page Write Operation:

–Active: 25 mA Max.

–Standby: 150

A Max.

Simple Write Operation:

–1 to 64 Bytes in 5ms

–Page Load Timer

End of Write Detection:

–On-Chip Address and Data Latches

–Self-Timed Write Cycle with Auto-Clear

Fast Write Cycle Time:

–Toggle Bit

–DATA Polling

100,000 Program/Erase Cycles

100 Year Data Retention

Commerical, Industrial and Automotive

–5ms Max

CMOS and TTL Compatible I/O

Temperature Ranges

DESCRIPTION

The CAT28C256 is a fast, low power, 5V-only CMOS

parallel E

PROM organized as 32K x 8-bits. It requires a

simple interface for in-system programming. On-chip

address and data latches, self-timed write cycle with auto-

clear and V

power up/down write protection eliminate

additional timing and protection hardware.

DATA

Polling

and Toggle status bits signal the start and end of the self-

timed write cycle. Additionally, the CAT28C256 features

hardware and software write protection.

The CAT28C256 is manufactured using Catalyst’s ad-

vanced CMOS floating gate technology. It is designed to

endure 100,000 program/erase cycles and has a data

retention of 100 years. The device is available in JEDEC

approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC

packages.

BLOCK DIAGRAM

A6–A14

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

ROW

DECODER

32,768 x 8

PROM

ARRAY

64 BYTE PAGE

VCC

HIGH VOLTAGE

GENERATOR

CONTROL

LOGIC

I/O BUFFERS

TIMER

DATA POLLING

AND

TOGGLE BIT

COLUMN

DECODER

5096 FHD F02

I/O0–I/O7

A0–A5

ADDR. BUFFER

& LATCHES

Characteristics subject to change without notice

Doc. No. 25020-0A 2/98

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