Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16500C
74ABTH16500C
FEATURES
•
18-bit bidirectional bus interface
•
3-State buffers
•
74ABTH16500C incorporates bus-hold data inputs which
•
Output capability: +64mA/-32mA
•
TTL input and output switching levels
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
Negative edge-triggered clock inputs
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
•
Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, or latched modes.
and 200V per Machine Model
eliminate the need for external pull-up resistors to hold unused
inputs
DESCRIPTION
The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Two options are available, 74ABT16500C which does not have the
bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
I
CCL
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
I/O pin capacitance
Quiescent su ly current
supply
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF;
V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
I/O
= 0V or V
CC
Outputs disabled; V
CC
= 5.5V
Outputs low; V
CC
= 5.5V
TYPICAL
2.1
1.7
3
7
500
8
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16500C DL
74ABT16500C DGG
74ABTH16500C DL
74ABTH16500C DGG
NORTH AMERICA
BT16500C DL
BT16500C DGG
BH16500C DL
BH16500C DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
1998 Feb 27
2
853-1800 19027
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16500C
74ABTH16500C
PIN DESCRIPTION
PIN NUMBER
1
27
2, 28
55,30
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
OEAB
OEBA
LEAB/LEBA
CPAB/CPBA
A0-A17
B0-B17
GND
V
CC
NAME AND FUNCTION
A-to-B Output enable input
B-to-A Output enable input (active low)
A-to-B/B-to-A Latch enable input
A-to-B/B-to-A Clock input (active falling edge)
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
OEAB
L
L
L
L
L
L
H
H
H
H
H
H
H
H
LEAB
H
↓
↓
L
L
L
H
H
↓
↓
L
L
L
L
CPAB
X
X
X
H or L
↓
↓
X
X
X
X
↓
↓
H or L
H or L
An
X
h
I
X
h
I
H
L
h
I
h
I
X
X
Internal
Registers
X
H
L
NC
H
L
H
L
H
L
H
L
H
L
OUTPUTS
Bn
Z
Z
Disabled,
Disabled Latch data
Z
Z
Z
Disabled,
Disabled Clock data
Z
H
Transparent
L
H
Latch data & display
L
H
Clock data & display
L
H
Hold data & display
L
NOTE:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off ” state
↓
= High-to-Low Enable or Clock transition
Disabled, Hold data
Disabled
OPERATING MODE
1998 Feb 27
4
Creative Market
京公网安备 11010802033920号
EEWORLD
