The ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs are in a high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
Inputs
OE
H
H
H
H
L
L
L
L
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
NC No Change
Internal
D
L
H
L
H
L
H
L
H
Q
NC
NC
L
H
L
H
NC
NC
Outputs
O
Z
Z
Z
Z
L
H
NC
NC
Hold
Hold
Load
Load
Function
CP
H or L
H or L
Data Available
Data Available
No Change in Data
No Change in Data
H or L
H or L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74ABT574
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.55
1
1
7
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
Min
Min
Min
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
64 mA
2.7V (Note 3)
V
CC
7.0V
0.5V (Note 3)
0.0V
1.9
P
A
P
A
P
A
P
A
V
Max
Max
Max
0.0
0
5.5V
0
5.5V
Max
Max
0.0
Max
Max
Max
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
10
P
A
P
A
mA
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
2.7V; OE
0.5V; OE
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
50
30
50
2.5
2.5
2.5
P
A
P
A
P
A
mA
5.5V; All Other GND
All Outputs HIGH
All Outputs LOW
OE
V
I
V
CC
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
P
A
mA
mA
mA
All Others at V
CC
or GND
Max
Enable Input V
I
Data Input V
I
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
Note 4:
For 8-bit toggling, I
CCD
0.8 mA/MHz.
No Load
0.30
mA/
MHz
Max
Outputs Open, OE
50% Duty Cycle
GND,
One Bit Toggling (Note 4),
3
www.fairchildsemi.com
74ABT574
DC Electrical Characteristics
(SOIC Package)
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Min
Typ
0.7
Max
1.0
Units
V
V
V
V
0.8
V
V
CC
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
T
A
T
A
T
A
T
A
T
A
50 pF, R
L
500
:
25
q
C (Note 5)
25
q
C (Note 5)
25
q
C (Note 6)
25
q
C (Note 7)
25
q
C (Note 7)
1.5
2.5
2.0
1.1
3.0
1.6
1.2
Note 5:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7:
Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
T
A
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
150
2.0
2.0
1.5
1.5
1.5
1.5
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
200
3.2
3.3
3.1
3.1
3.6
3.4
5.0
5.0
5.3
5.3
5.4
5.4
Max
T
A
55
q
C to
125
q
C
4.5V to 5.5V
50 pF
Max
7.0
7.4
6.5
7.2
7.2
6.7
C
L
Min
150
1.5
1.5
1.0
1.0
1.0
1.0
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
C
L
50 pF
Max
MHz
5.0
5.0
5.3
5.3
5.4
5.4
ns
ns
ns
Units
V
CC
Min
150
2.0
2.0
1.5
1.5
1.5
1.5
AC Operating Requirements
T
A
Symbol
Parameter
V
CC
C
L
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH
or LOW D
n
to CP
Hold Time, HIGH
or LOW D
n
to CP
Pulse Width, CP,
HIGH or LOW
1.0
1.5
1.0
1.0
3.0
3.0
25
q
C
5.0V
50 pF
Max
T
A
55
q
C to
125
q
C
4.5V to 5.5V
C
L
Min
1.5
2.0
2.0
2.0
3.3
3.3
50 pF
Max
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
ns
ns
ns
C
L
Units
V
CC
Min
1.0
1.5
1.0
1.0
3.0
3.0
www.fairchildsemi.com
4
74ABT574
Extended AC Electrical Characteristics
(SOIC Package)
T
A
V
CC
Symbol
Parameter
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
C
L
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
250 pF
C
L
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
250 pF
Units
C
L
8 Outputs Switching
(Note 8)
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
CP to O
n
Output Enable Time
1.5
1.5
1.5
1.5
1.0
1.0
Max
5.7
5.7
6.2
6.2
5.5
5.5
(Note 9)
Min
2.0
2.0
2.0
2.0
(Note 11)
Max
7.8
7.8
8.0
8.0
8 Outputs Switching
(Note 10)
Min
2.0
2.0
2.0
2.0
Max
10.0
10.0
10.5
10.5
ns
ns
ns
(Note 11)
Note 8:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11:
The 3-STATE Delay Times are dominated by the RC network (500
:
, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 12)
(SOIC package)
T
A
40
q
C to
85
q
C
4.5V–5.5V
50 pF
C
L
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
Units
C
L
V
CC
Symbol
Parameter
V
CC
8 Outputs Switching
(Note 12)
Max
t
OSHL
(Note 14)
t
OSLH
(Note 14)
t
PS
(Note 15)
t
OST
(Note 14)
t
PV
(Note 16)
Pin to Pin Skew
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
LH–HL Skew
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
1.0
1.0
1.8
2.0
2.5
8 Outputs Switching
(Note 13)
Max
1.8
1.8
4.3
4.3
4.6
ns
ns
ns
ns
ns
Note 12:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). This specification is guaranteed but not tested.
Note 15:
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16:
Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
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