HC705V8GRS/D
REV 2.1
68HC705V8
SPECIFICATION
REV 2.1
(General Release)
©
August 12, 1994
MCU System Design Group
Oak Hill, Texas
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
MC68HC705V8 Specification Rev. 2.1
TABLE OF CONTENTS
SECTION 1
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10
1.5.11
1.5.12
1.5.13
1.5.14
1.5.15
1.5.16
1.5.17
GENERAL DESCRIPTION .............................................. 1
FEATURES.................................................................................1
MASK OPTIONS ........................................................................2
PIN ASSIGNMENTS...................................................................2
MCU STRUCTURE ....................................................................8
FUNCTIONAL PIN DESCRIPTION ............................................9
V
BATT
/V
PP
.............................................................................9
V
DD
AND V
SS
........................................................................9
V
SSA1
.....................................................................................9
V
SSA2
.....................................................................................9
V
CCA
......................................................................................9
V
REFH
AND V
REFL
.................................................................9
OSC1, OSC2.......................................................................10
RESET ................................................................................ 11
IRQ (MASKABLE INTERRUPT REQUEST) .......................11
PA0-PA7..............................................................................11
PB0-PB5, PB6/TCMP, PB7/TCAP ......................................11
PC0-PC7 .............................................................................11
AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7 ........................12
PWM....................................................................................12
PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO .........................12
BUS, LOAD, REXT1, REXT2 ..............................................12
V
IGN
.....................................................................................13
SECTION 2
2.1
2.2
2.3
2.4
2.5
2.6
MEMORY MAP .............................................................. 15
SINGLE-CHIP MODE MEMORY MAP .....................................15
I/O AND CONTROL REGISTERS ............................................15
RAM..........................................................................................16
BOOTROM ...............................................................................17
EPROM.....................................................................................17
EEPROM ..................................................................................17
SECTION 3
3.1
3.1.1
3.2
3.2.1
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
EPROM AND EEPROM ................................................. 23
EPROM BOOTLOADER...........................................................23
BOOTLOADER FUNCTIONS .............................................23
EPROM PROGRAMMING........................................................23
PROGRAMMING REGISTER $0D .....................................24
MASK OPTION REGISTER (MOR) $3C00 ..............................25
EEPROM PROGRAMMING REGISTER $1C ..........................27
CPEN - Charge Pump Enable.............................................27
ER1:ER0 - Erase Select Bits...............................................27
LATCH.................................................................................28
EERC - EEPROM RC Oscillator Control .............................28
MOTOROLA
Page iii
MC68HC705V8 Specification Rev. 2.1
3.4.5
3.5
EEPGM - EEPROM Programming Power Enable .............. 28
OPERATION IN STOP AND WAIT .......................................... 30
SECTION 4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
CPU CORE .....................................................................31
REGISTERS............................................................................. 31
ACCUMULATOR (A) .......................................................... 31
INDEX REGISTER (X) ........................................................ 31
STACK POINTER (SP) ....................................................... 32
PROGRAM COUNTER (PC) .............................................. 32
CONDITION CODE REGISTER (CCR) .............................. 32
SECTION 5
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.6
5.7
5.8
5.9
INTERRUPTS .................................................................35
CPU INTERRUPT PROCESSING ........................................... 35
RESET INTERRUPT SEQUENCE........................................... 38
SOFTWARE INTERRUPT (SWI) ............................................. 38
HARDWARE INTERRUPTS..................................................... 38
EXTERNAL INTERRUPT (IRQ) ............................................... 38
IRQ CONTROL/STATUS REGISTER (ICSR) $1F ............. 40
EXTERNAL INTERRUPT TIMING ...................................... 42
16-BIT TIMER INTERRUPT ..................................................... 43
MDLC INTERRUPT.................................................................. 43
SPI INTERRUPT ...................................................................... 43
8-BIT TIMER INTERRUPT ....................................................... 44
SECTION 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
RESETS..........................................................................45
EXTERNAL RESET (RESET) .................................................. 45
INTERNAL RESETS ................................................................ 46
POWER-ON RESET (POR)................................................ 46
OPERATION IN STOP AND WAIT ..................................... 46
COMPUTER OPERATING PROPERLY RESET (COPR) .. 48
LOW-VOLTAGE RESET (LVR) .......................................... 49
ILLEGAL ADDRESS ........................................................... 50
DISABLED STOP INSTRUCTION ...................................... 50
SECTION 7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.4.1
7.5
7.5.1
MOTOROLA
Page iv
POWER SUPPLY AND REGULATION .........................51
INTERNAL POWER SUPPLY .................................................. 51
PRIMARY 5V REGULATOR ............................................... 51
SECONDARY REGULATOR .............................................. 51
MISCELLANEOUS REGISTER ............................................... 52
IGNS - Ignition status bit ..................................................... 52
OCE - Output compare enable ........................................... 52
PDC - Power Down Control ................................................ 52
POWER MODING .................................................................... 53
REGULATOR CONTROL LOGIC ............................................ 55
MASK OPTIONS................................................................. 56
POWER SUPPLY CONFIGURATION...................................... 59
DECOUPLING RECOMMENDATIONS .............................. 59
MC68HC705V8 Specification Rev. 2.1
SECTION 8
8.1
8.1.1
8.1.2
LOW-POWER MODES .................................................. 63
STOP INSTRUCTION ..............................................................63
STOP MODE .......................................................................63
WAIT INSTRUCTION ..........................................................65
SECTION 9
9.1
9.1.1
9.1.2
9.1.3
9.2
9.2.1
9.2.2
9.3
9.4
9.4.1
9.4.2
PARALLEL I/O............................................................... 67
PORT A AND PORT C .............................................................67
PORT A/C DATA REGISTERS............................................67
PORT A/C DATA DIRECTION REGISTER .........................68
PORT A/C I/O PIN INTERRUPTS.......................................68
PORT B ....................................................................................68
PORT B DATA REGISTER..................................................69
PORT B DATA DIRECTION REGISTER .............................69
PORT D AND PORT E .............................................................69
PORT F.....................................................................................70
PORT F DATA REGISTER..................................................70
PORT F DATA DIRECTION REGISTER .............................70
SECTION 10
10.1
10.1.1
10.1.2
10.1.3
10.2
10.3
10.4
10.5
10.6
10.7
A/D CONVERTER.......................................................... 71
ANALOG SECTION..................................................................71
RATIOMETRIC CONVERSION ..........................................71
V
REFH
AND V
REFL
...............................................................71
ACCURACY AND PRECISION ...........................................71
CONVERSION PROCESS .......................................................71
DIGITAL SECTION...................................................................71
A/D STATUS AND CONTROL REGISTER (ADSCR) ..............72
A/D DATA REGISTERS ...........................................................73
A/D DURING WAIT MODE .......................................................74
A/D DURING STOP MODE ......................................................74
SECTION 11
11.1
11.2
11.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.5
11.5.1
11.5.2
11.5.3
11.5.4
16-BIT TIMER ................................................................ 75
COUNTER REGISTER - $18:$19, $1A:$1B.............................76
OUTPUT COMPARE REGISTER - $16:$17 ............................76
INPUT CAPTURE REGISTER - $14:$15 .................................77
TIMER CONTROL REGISTER (TCR) - $12.............................78
ICIE - Input Capture Interrupt Enable..................................78
OCIE - Output Compare Interrupt Enable ...........................78
TOIE - Timer Overflow Interrupt Enable ..............................78
TON - Timer On...................................................................78
IEDG - Input Edge ...............................................................78
OLVL - Output Level............................................................79
TIMER STATUS REGISTER (TSR) - $13 ................................79
ICF - Input Capture Flag......................................................79
OCF - Output Compare Flag ...............................................79
TOF - Timer Overflow Flag..................................................79
Bits 0-4 - Not used...............................................................79
MOTOROLA
Page v
MC68HC705V8 Specification Rev. 2.1
11.6
11.7
TIMER DURING WAIT MODE ................................................. 80
TIMER DURING STOP MODE................................................. 80
SECTION 12
12.1
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
12.1.7
12.2
12.3
12.4
CORE TIMER .................................................................81
CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08.... 82
CTOF - Core Timer Over Flow............................................ 82
RTIF - Real Time Interrupt Flag .......................................... 82
TOFE - Timer Over Flow Enable......................................... 82
RTIE - Real Time Interrupt Enable...................................... 82
TOFC - Timer Over Flow Flag Clear ................................... 82
RTFC - Real Time Interrupt Flag Clear ............................... 83
RT1:RT0 - Real Time Interrupt Rate Select ........................ 83
COMPUTER OPERATING PROPERLY (COP) RESET .......... 83
CORE TIMER COUNTER REGISTER (CTCR) $09 ................ 84
TIMER DURING WAIT MODE ................................................. 84
SECTION 13
13.1
13.2
13.2.1
13.2.2
13.3
13.4
13.5
PULSE WIDTH MODULATOR.......................................85
FUNCTIONAL DESCRIPTION ................................................. 85
REGISTERS............................................................................. 86
PWM CONTROL................................................................. 87
PWM DATA REGISTERS ................................................... 88
PWM DURING WAIT MODE.................................................... 88
PWM DURING STOP MODE ................................................... 88
PWM DURING RESET ............................................................ 88
SECTION 14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.2
14.3
14.3.1
14.3.2
14.3.3
14.4
14.5
SERIAL PERIPHERAL INTERFACE .............................89
SPI SIGNAL DESCRIPTION .................................................... 89
Master In Slave Out (MISO/PF3) ........................................ 90
Master Out Slave In (MOSI/PF2) ........................................ 90
Serial Clock (SCK/PF1) ...................................................... 90
Slave Select (SS/PF0) ........................................................ 91
FUNCTIONAL DESCRIPTION ................................................. 91
SPI REGISTERS ...................................................................... 93
Serial Peripheral Control Register (SPCR) ......................... 93
Serial Peripheral Status Register (SPSR)........................... 94
Serial Peripheral Data I/O Register (SPDR) ....................... 95
SPI IN STOP MODE ............................................................... 96
SPI IN WAIT MODE ................................................................. 96
SECTION 15
15.1
15.1.1
15.1.2
15.2
15.2.1
15.2.2
15.2.3
MOTOROLA
Page vi
MESSAGE DATA LINK CONTROLLER.......................97
OUTLINE .................................................................................. 98
MDLC OPERATING MODES.............................................. 99
MODE DESCRIPTIONS ..................................................... 99
MDLC CPU INTERFACE ....................................................... 101
OUTLINE .......................................................................... 101
MDLC CONTROL REGISTER (MCR) $0E ....................... 102
MDLC STATUS REGISTER (MSR) $0F........................... 105
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